Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-16
2002-05-14
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S324000, C257S411000
Reexamination Certificate
active
06388293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory cell, a nonvolatile memory array and a method of operating the same, and more particularly to a nonvolatile memory cell and/or array and a method of operating the same enabling high integration density, low voltage programming and/or high speed programming.
A MNOS memory is one of typical semiconductor memories wherein carrier charge is stored in a gate insulator to have information nonvolatilely stored. The MNOS memory is of a laminated structure comprising a conductive gate (M), a silicon nitride film (N), a tunnel oxide film (O) and a semiconductor wherein the carrier (electron or hole) is captured at a trapping level in the silicon nitride film to store the carrier charge. In this step, the silicon nitride film of the MNOS memory was required to be more than 19 nm in thickness since the charge trapping efficiency depended on the carrier capture distance in the silicon nitride film (Document 1: F. L. Hampton and J. R. Cricchi “Space charge distribution limitation of scale down of MNOS devices”, 1979
IEDM Technical Digest
, p. 374).
To program (write or erase) the MNOS memory, at least more than 10V or about 20V as a normal value of programming voltage was required for a electric field to be fed to a semiconductor surface via the silicon nitride film so that a carrier may be injected in the nitride film through (via a tunnel) the tunnel oxide film.
Also, a MONOS memory is disclosed as the nonvolatile memory capable of reducing the programming voltage (Document 2: E. Suzuki, H. Hiraishi, K. Ishii and Y. Hayashi, “A Low-Voltage Alterable EEPROM with Metal-Oxide-nitride-Oxide and semiconductor (MONOS) Structures”,
IEEE Transaction on Electron Devices
, Vol. ED-30, February 1983, p. 122). This MONOS memory is of a laminated structure comprising a conductive gate (M), a top oxide film (O), a silicon nitride film (N), a tunnel oxide film (O) and semiconductor. This structure has enabled the MONOS memory to stop hopping via the carrier trapping level in the silicon nitride film due to a potential barrier formed between the nitride film and the top oxide film, which resulted in making the nitride film as thin as possible. Further, carrier traps newly generated at the interface between the top oxide film and nitride film has enlarged a memory window to the extent it is possible to identify the stored information even if the entire insulator thickness is made thinner.
This MONOS memory has made it possible to reduce the programming voltage down to 9V with the usable programming speed (0.1 msec) under the condition that the stored information is maintained for ten years (Document 3: T. Nozaki, T. Tanaka, Y. Kijiya, E. Kinoshita, T. Tsuchiya and Y. Hayashi, “A1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application”,
IEEE Journal of Solid-State Circuits
, Vol. 26, No. 4, April, 1991, p. 497).
It has yet to be disclosed, however, whether or not it is possible to reduce a programming voltage to be less than 9V under the condition that the programming speed is less than 0.1 msec and memory retention characteristics are maintained. To achieve the programming voltage of less than 9V, either programming speed or memory storage characteristics or both were required to be sacrificed.
Disclosed is a technology to integrate a single transistor cell with a single gate (to be connected to a word line) in the form of an array to improve integration density which is more excellent than that disclosed in the Document 3 as described above. However, since it was required to supply electrical potential to not only a drain region but also a source region so as not to write in an unselected cell which results in separately connecting both drain and source regions to a bit line direction, it was impossible to improve the integration density even if a single gate structured single transistor cell is used therein. (Document 4: 1. Fujiwara, H. Aozasa, A. Nakamura, Y. Komatsu, and Y. Hayashi, “0.13 &mgr;m MONOS single transistor memory cell with separated source”, 1998
IEDM Technical Digest
, 36.7, p995-998, FIG.
2
&
11
).
When integrating a single gate cell in the form of an array to read the stored information, there is deterioration of memory retention characteristics called “read disturb” since electrical potential for reading the stored information is to be supplied to a gate.
To prevent the deterioration of the retention characteristics as described above and to keep the stored information well trapped even in the state of electrical potential being supplied to a gate, it was required to increase the thickness of the above-indicated tunnel oxide film from 2.0 nm to 2.7 nm. To make as minimal as possible the programming speed deterioration due to the increase of a tunnel oxide film thickness, it was necessary to increase programming voltage from 9V to 12V.
Meanwhile, disclosed is technology of ballistic carrier injection for a floating gate memory cell which is intended to enable reduction of programming voltage and increase of programming speed (Document 5: S. Ogura, A. Hori, J. Kato, M. Yamanaka, S. Odanaka, H. Fujimoto, K. Akamatsu, T. Ogura, M. Komiya and H. Kotani, “Low voltage, Low current, High speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash”, 1998
IEDM Technical Digest
, 36.5, p.987-990). The ballistic carrier injection as described above has such a configuration that formed in the form of a step in a surface of a semiconductor substrate is a thin drain region through which a hot carrier is ballistically transported to a floating gate and the floating gate is disposed to cover the step portion. This improves the injection efficiency since the speed component in the carrier transport direction contributes to generating energy for the carrier injection.
However, the carrier injection and discharge of a conventional MONOS nonvolatile memory are carried out in an entire surface of a channel forming a semiconductor region beneath a gate insulator in which carrier charge trapping function is incorporated and it was not known from the carrier injection in a floating gate memory cell whether or not current or voltage sensed at time of reading the memory cell was controlled by the carrier charge in the gate insulator trapped by local carrier injection in source/drain directions in a channel forming semiconductor region. Neither was it possible to clearly read that the carrier charge injected through the above-mentioned thin drain resulted in changing current and voltage in the conventional MONOS nonvolatile memory.
With respect to a conventional floating gate memory, it is liable to cause defective bits if even one location of a gate insulator is found to be defective which results in deteriorating the memory retention characteristics of an entire cell. In addition, the ratio of the total capacitance of a floating gate to the capacitance between a control gate and floating gate decreases as a memory structure becomes fine. To eliminate the disadvantage as described above, it was required to adopt such a structure as to increase the overlapped area between the control gate and floating gate and further, there was no choice but to increase a number of manufacturing process steps and cell area.
SUMMARY OF THE INVENTION
It is a purpose of the present invention to resolve problems in the conventional technology and provide a nonvolatile memory cell which is not only capable of programming with lower voltage but also has a remote possibility of causing defective bits and has fewer manufacturing process steps compared to a conventional floating gate memory; a method of using the same and a nonvolatile memory array.
To achieve the purpose as described above, the present invention is provided with the means featured below:
A nonvolatile memory cell wherein first and second impurity regions of opposite conductivity type are formed in a main surface of a substrate and separated therebetween by a channel forming semiconductor region of one conductivity typ
Hayashi Yutaka
Ogura Seiki O.
Ackerman Stephen B.
Halo LSI Design & Device Technology, Inc.
Pike Rosemary L. S.
Pizarro-Crespo Marcos D.
Saile George O.
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