Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-18
2002-05-14
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S544000, C257S655000, C438S275000
Reexamination Certificate
active
06388295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOS (Metal Oxide Silicon) semiconductor device and a method of manufacturing the same, and particularly a semiconductor device provided with wells having different depths as well as a method of manufacturing the same.
2. Description of the Background Art
In accordance with advances in design technology and process technology, it is now becoming possible to manufacture a high-density integrated circuit provided with a plurality of integrated circuits, which are the same as those manufactured independently of each other in the prior art, on a single chip. It is now becoming possible to produce a structure, in which a semiconductor device such as a DRAM (Dynamic Random Access Memory) as well as a high-density integrated logic circuit such as an MPU (Micro Processing Unit) are formed in a single chip. For manufacturing such integrated circuits, it is necessary to arrange within a single chip a plurality of MOS field-effect elements having different structures according to purposes.
A semiconductor device in which memory cells and a peripheral circuit are formed on a common substrate is disclosed, e.g., in Japanese Patent Laying-Open Nos. 4-212453 and 5-267606. These publications have disclosed semiconductor devices, in which a p-well region provided with memory cell transistors is surrounded by an n-region.
FIG. 50
is a cross section showing elements of a semiconductor device in the prior art. In
FIG. 50
,
101
indicate a p-type semiconductor substrate,
102
indicates an isolating and insulating film,
103
indicates an n-well and
104
indicates a p-well. According to this structure, in which p-well
104
of a memory cell part is surrounded by n-wells
103
and thereby is electrically isolated from the peripheral circuit part, the potential on p-well
104
can be determined independently, and n-wells
103
surrounding p-well
104
intercept electrons coming from p-type semiconductor substrate
101
so that soft error can be prevented.
For providing a deeper well, however, it is necessary to provide a wider region, which is not provided with a transistor, in the well end. In accordance with further miniaturization of the semiconductor integrated circuit, therefore, an isolation width and a width of the well are reduced, and the depth of the well is reduced. Thereby, the impurity concentration of the well increases, and the impurity concentration at the surface of the semiconductor substrate increases, resulting in a problem of deterioration of element characteristics such as increase in junction leak current. For suppressing the junction leak current, the impurity concentration of the well may be reduced. However, this results in a problem of increase in well resistance. Particularly in the memory cell region, the junction leak current deteriorates refresh characteristics.
SUMMARY OF THE INVENTION
The invention has been developed for overcoming the above problems, and it is an object to provide a semiconductor device, in which a semiconductor integrated circuit can be miniaturized while providing a memory cell region having improved refresh characteristics as well as a logic circuit having including shallow wells and therefore including miniaturized circuits capable of achieving required performances, and can achieve intended respective performances. It is also an object of the invention to provide a method of manufacturing such a semiconductor device.
It is an object of the invention to provide a semiconductor device, in which refresh characteristics are improved in a memory cell region, relatively shallow wells are employed in a logic circuit region for miniaturizing a circuit structure, and thereby performances required in the respective regions can be achieved in the miniaturized semiconductor integrated circuit having the memory cell region and the logic circuit region, as well as a method of manufacturing the semiconductor device.
For achieving the above object, a semiconductor device according to an aspect of the invention includes a semiconductor layer of a first conductivity type; a first impurity region of a second conductivity type formed at a main surface of the semiconductor layer and having a first impurity concentration peak; a second impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the first impurity region, and having a second impurity concentration peak at a smaller depth than the first impurity concentration peak; a third impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located within the planar region provided with the first impurity region, surrounding the second impurity region, and having a third impurity concentration peak at a smaller depth than the first impurity concentration peak; a fourth impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region spaced from the first impurity region, and having a fourth impurity concentration peak; a fifth impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the fourth impurity region, and having a fifth impurity concentration peak at a smaller depth than the second and fourth impurity concentration peaks; a sixth impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the fourth impurity region, surrounding the fifth impurity region and having a sixth impurity concentration peak at a smaller depth than the fourth impurity concentration peak; a first field-effect element of the second conductivity type formed at the main surface of the second impurity region; and a second field-effect element of the second conductivity type formed at the main surface of the fifth impurity region.
Owing to the above structure, a triple well structure can be employed for allowing setting of the substrate potential of the element independently of the semiconductor substrate while suppressing a junction leak current by the second impurity region, and allowing miniaturization by the fifth impurity region.
In the semiconductor device of the above aspect, the first impurity concentration peak and the fourth impurity concentration peak may be formed at the substantially equal depths from the main surface of the semiconductor layer, respectively. Thus, the first and fourth impurity regions may have the substantially same impurity concentration distributions in the direction of the substrate depth, whereby the semiconductor device having the triple well structure suitable to the multifunction configuration can be achieved through simple steps.
In this case, the first and third impurity regions may be spaced by a predetermined distance from each other in a direction of a depth determined from the main surface of the semiconductor layer, and the fourth and sixth impurity regions may be spaced by a predetermined distance from each other in the direction of the depth determined from the main surface of the semiconductor layer. According to the above structure, the semiconductor device having the triple well structure suitable to the multifunction configuration can be obtained while suppressing increase in number of steps.
According to an embodiment of the above aspect, the semiconductor device further includes a seventh impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the first impurity region, surrounding the second impurity region, and having a seventh impurity concentration peak located shallower than the first impurity concentration peak and deeper than the third impurity concentration peak and being lower in concentration than the first and third impurity concentration peaks; and an eighth impurity region of the second conductivity type formed at the main surf
Hachisuka Atsushi
Okumura Yoshinori
Soeda Shinya
Yamashita Tomohiro
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