Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-04
2002-08-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S642000, C438S639000, C438S638000, C438S637000, C438S239000, C438S243000, C257S068000, C257S071000
Reexamination Certificate
active
06429123
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor process, and more specifically, to a method of defining sidewall spacers repeatedly to form a plurality of buried metal line array on substrate.
BACKGROUND OF THE INVENTION
With the advance of integrated circuits technology into the ultra large scale integrated circuits (ULSI), the sizes of various devices have gotten smaller and smaller in order to manufacture the devices and the integrated circuits with high integration. However, when the scales of devices are getting smaller, many technical difficulties occur in performing the semiconductor processes. And the complexes of processes are also increasing.
In general, the key factor of techniques about integrated circuit designs is lithography process. Wherein the patterns of reticles can be transferred to the semiconductor substrate by using the lithography process to define patterns onto the material layers thereon and to frame the whole circuits structures. However as the sizes of devices continued shrinking, it is very difficult to pattern the reticles. And the difficulties to define fine patterns on substrate increases due to the restrictions such as the resolutions of lithography, the precision of pattern transferring, and the smaller space for using.
Especially for the integrated circuits, more than million devices and connections will be formed in the narrow and small area. Therefore various material layers and functional layers are stacked on the substrate in succession to form and define the desired devices. But when the density of these devices are increasing, the gaps among these devices are also getting narrow. Thus there are plenty of challenges encountered in manufacturing the metal lines to connect the devices.
Besides, the operating voltages, electric currents, and resistance of those devices must be controlled more critically to satisfy the fine integration circuits. So the areas of metal lines are increasing as large as possible to reduce the resistance therein and to promote the electric communications. However when the areas of metal patterns are too large, it is very difficult to manufacture other devices thereon. Thus how to form the metal patterns with large areas but occupying smaller space is becoming the important issue in the current semiconductor processes.
SUMMARY OF THE INVENTION
A method for manufacturing a plurality of buried metal lines on a semiconductor substrate is provided in this invention. The method comprises the following steps. First, a dielectric layer is formed on a semiconductor substrate. And a first insulator layer is formed on the dielectric layer to serve as an etching stop layer. Then, a second insulator layer is formed on the first insulator layer. And an etching procedure is done to etch the second insulator layer to define a plurality of insulator blocks on the first insulator layer, wherein each the insulator block has a width of 3 unit (3×), and each gap between two adjacent the insulator blocks has a width of 5 unit (5×). A first layer is deposited on outer surfaces of the insulator blocks, wherein the first layer has a width of 1 unit (1×). The first layer is next etched to form first sidewall spacers on sidewalls of the insulator blocks. And the plurality of the insulator blocks are removed, wherein each gap between two adjacent the first sidewall spacers has a width of 3 unit (3×). A second layer is deposited on outer surfaces of the first sidewall spacers, wherein the second layer has a width of 1 unit (1×). The second layer is etched to form second sidewall spacers on sidewalls of the first sidewall spacers. And a third layer is formed on outer surfaces of the second sidewall spacer and the first sidewall spacer, wherein materials of the third layer and the first layer are same, and the third layer has a width of 1 unit (1×). The third layer is then etched to form studs into gaps between two adjacent the second sidewall spacers, and to form third sidewall spacers on sidewalls of the peripheral second sidewall spacer. The second sidewall spacers are removed by using a selective etching to form gaps between adjacent the first sidewall spacer and the stud, wherein the gap has 1 unit (1×). The first insulator layer and the dielectric layer are etched to form a plurality of trenches in the dielectric layer by using said first sidewall spacers, the third sidewall spacers and the studs to serve as etching masks. The first sidewall spacers, the studs, the third sidewall spacers, and the first insulator layer are removed. And a metal layer is deposited to fill into the trenches to form a plurality of metal lines.
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Blakely , Sokoloff, Taylor & Zafman LLP
Lee Granvill D
Smith Matthew
Vanguard International Semiconductor Corporation
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