Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1999-11-23
2002-08-13
Ho, Hoai V. (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S787000, C438S638000
Reexamination Certificate
active
06432845
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a multiple-wiring-layer structure and a method for manufacturing the same.
2. Description of Related Art
In a semiconductor device having a multiple-wiring-layer structure, insulation between wiring layers is provided by interlayer dielectric films. Techniques for forming interlayer dielectric films are described in, for example, Japanese Laid-open patent applications HEI 7-86284 and HEI 7-161703.
These interlayer dielectric films disclosed in the above references have internal compression stress. This results in warping of a semiconductor wafer when semiconductor devices are manufactured. The warping of the semiconductor wafer creates various problems in manufacturing of semiconductor devices. For example, a semiconductor wafer is mounted on a vacuum chuck while thin films (interlayer dielectric films, metal wiring layers, etc.) are formed. If the semiconductor wafer is warped, heat is not uniformly conducted through the semiconductor wafer. As a result, the thickness of the thin film thus formed is not uniform. In many occasions, many interlayer dielectric films are formed in between the wiring layers. As a result, more wiring layers result in a greater number of interlayer dielectric films. As a consequence, the compression stress in the semiconductor wafer increases, with the result that the warping of the semiconductor wafer becomes greater.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having a structure that is capable of reducing warping of a semiconductor wafer when the semiconductor device is manufactured. It is also an object of the present invention to provide a method for manufacturing the same.
In accordance with one embodiment of the present invention, a semiconductor device has a semiconductor substrate having a main surface, at least one wiring layer formed over the main surface, and interlayer dielectric films formed over the at least one wiring layer or between the main surface and the at least one wiring layer. At least one of the interlayer dielectric films includes a first film having an internal tensile stress, and at least another of the interlayer dielectric films includes a second film having an internal compression stress.
In accordance with one embodiment of the present invention, the semiconductor device is manufactured by a method comprising at least the steps of: (a) forming the first film having an internal tensile stress by reacting a silicon compound with hydrogen peroxide by a CVD method; and (b) forming the second film having an internal compression stress by a CVD method.
In accordance with one embodiment of the present invention, in step (a), the first film is a silicon oxide film. When the silicon oxide film is formed by reacting a silicon compound with hydrogen peroxide by a CVD method, the film has an internal tensile stress. On the other hand, in step (b), the second film formed by a CVD method is a silicon oxide film having an internal compression stress. As a result, the tensile stress and the compression stress in the interlayer dielectric films act on the semiconductor wafer when the semiconductor device is manufactured. Accordingly, an overall stress that acts on the semiconductor wafer becomes small or zero (0). Therefore, warping of the semiconductor wafer is reduced or eliminated when the semiconductor device is manufactured. It is noted that step (a) and step (b) can be performed in any order. In other words, step (a) can be performed first, or step (b) can be performed first.
CVD methods that cause internal compression stresses in a formed film include, for example, pyrolysis or hydrolysis of organic oxysilane, and plasma CVD method or reduced pressure CVD method that utilizes oxidation of silane.
After step (b), the interlayer dielectric film including the second silicon oxide film may preferably be polished by chemical-mechanical polishing (CMP). As a result, the interlayer dielectric film including the second silicon oxide film is planarized.
A through hole may be formed in the interlayer dielectric film including the second silicon oxide film. A high melting point metal, such as tungsten, may preferably be used as a conductive layer to fill in the through hole formed in the interlayer dielectric film including the second silicon oxide film.
In step (a), the first silicon oxide film may be formed by reacting a silicon compound and hydrogen peroxide utilizing a CVD method. As a result, the formed layer has an excellent planarization characteristic. More specifically, the first silicon oxide film formed in step (a) has a high flowability itself and a high self-planarization characteristic. This phenomenon is believed to take place due to the following mechanism. When a silicon compound and hydrogen peroxide are reacted by the CVD method, silanol is formed in vapor phase, and the silanol deposits on the surface of the wafer to provide a film having a high flowability.
For example, when monosilane is used as a silicon compound, silanol is formed by reactions defined by formulae (1) and (1)′ as follows:
SiH
4
+2H
2
O
2
→Si(OH)
4
+2H
2
Formula (1)
SiH
4
+3H
2
O
2
→Si(OH)
4
+2H
2
O+H
2
Formula (1)′
Silanol formed by the reactions defined by Formulae (1) and (1)′ becomes silicon oxide as a result of disconnection of water by polycondensation reaction defined by Formula (2) as follows:
Si(OH)
4
→SiO
2
+2H
2
O Formula (2)
The silicon compounds include, for example, inorganic silane compounds, such as monosilane, disilane, SiH
2
Cl
2
, SiF
4
and the like, and organo silane compounds, such as CH
3
SiH
3
, tripropyle-silane, tetraethylorthosilicate and the like.
The film formation in step (a) described above may preferably be conducted by a reduced pressure CVD method at temperatures of about 0-20° C. when the silicon compound is an inorganic silicon compound, and at temperatures of about 0-150° C. when the silicon compound is an organic silicon compound. If the temperature during the film-forming step is higher than the upper limit of the above-described temperature ranges, the polycondensation reaction defined by Formula (2) progresses excessively. As a result, the flowability of the first silicon oxide film lowers and therefore it is difficult to obtain good planarization. On the other hand, if the temperature is lower than the lower limit of the above-described temperature ranges, the control of a film forming apparatus becomes difficult. For example, adsorption of cracked water content occurs within the chamber and dew condensation occurs outside the chamber.
The first silicon oxide film formed in step (a) may preferably be formed with a thickness that sufficiently covers step differences of the underlying layer. The minimum thickness of the first silicon oxide film depends on the height of protrusions and recesses of the underlying layer, and is preferably between about 300 and about 1000 nm. If the film thickness of the first silicon oxide film exceeds over the above-described upper limit, cracks may occur due to stresses of the film itself.
The interlayer dielectric film in accordance with embodiments of the present invention may have a single layered structure or a multiple layered structure. In the case of a multiple layered structure having multiple interlayer dielectric films, one of the interlayer dielectric films may have an internal compression stress and another of the layers may have an internal tensile stress. As a result, the interlayer dielectric films in the multiple layered structure as a whole may have an internal tensile stress or an internal compression stress.
In accordance with another embodiment of the present invention, a semiconductor device comprises a semiconductor substrate having a main surface, a plurality of wiring layers over the main surface, and interlayer dielectric films formed between the main surface and the plurality of wiring
Ho Hoai V.
Hogan & Hartson L.L.P.
Le Thao P.
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