Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-02-15
2002-08-13
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S152000, C711S156000
Reexamination Certificate
active
06434675
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for controlling a storage device and, more particularly, to a method and apparatus for controlling a write processing operation when a plurality of processors generate write requests in parallel.
In communication system such as ATM (Asynchronous Transfer Mode) or the like, a plurality of data processing means such as processors perform various processing operations using external or internal storage units.
In these systems, it is important to keep track of data among a plurality of storage units with contents related to each other when the plurality of processors issue requests in parallel for write processing in the storage units. In addition, when the plurality of data processors are about to simultaneously use stored data for each write request, the data processors must prioritize or matching of data along the time axis must be ensured. That is, when a plurality of write requests are generated, the latest data must always be preferentially overwritten.
A general parallel write control method by a plurality of data processor for a plurality of storage units will be described below by way of some examples.
In one example, counter values “0” to “3” are described in tables corresponding to identifiers included in the headers of communication cells such as ATM cells. For convenience, one identifier is corresponds to an index for referring to a table. The entity of this table is stored in a main storage unit outside the communication apparatus.
Every time a cell having an identifier which has not been used for internal processing yet is received by the communication apparatus at a predetermined period (a period shorter than a long processing period on the host side), a copy of the data stored in the main storage unit with an index corresponding to the identifier is stored in a storage unit of the communication apparatus and, more specifically, a cache memory. Upon completion of this processing operation of a cell having the same identifier, the content written in the cache memory is rewritten in the main storage unit.
On the host side, a second data processor increments the counter values of the tables corresponding to all indices in the main storage unit by one at a predetermined period (long period). In the communication apparatus, every time a cell is received, a first data processor loads a table corresponding to the identifier from index data in the cache memory and initializes the counter value to “0”, thereby updating the data in the main storage unit of the cache memory.
The second data processor independently performs write processing operations in the main storage unit. The first data processor independently performs processing for the cache memory. Therefore, unless stored data having the same index are written in overlapping time periods, matching of these stored data is not degraded by the write processing operations in the main storage unit and the cache memory.
However, the main storage unit and the cache memory have the relationship between an entity (original data) and a duplicate (a copy of the original data). When stored data having the same index are independently written in the main storage unit and the cache memory in overlapping time periods, matching of these stored data may be degraded in a rewrite processing operation of the contents stored in the cache memory in the main storage unit.
Assume that the counter value of the table is “1”, and the second data processor increments the counter value to “2”. The second data processor refers to the table in the main storage unit that increments the counter value. At this time point, the counter value of the table is still “1”. The second data processors loads the counter value “1”, increments the counter value by one, and writes “2” in the table of the main storage unit.
In some cases, communication cells having identifiers representing the same index are received by the communication apparatus while the second data processors loads the table and rewrites the counter value. If the first data processor has initialized the counter value to “0”, the counter value “2” rewritten by the second data processor is based on the counter value “1”, i.e., the old data before being processed by the first data processor. For this reason, the second data processor overwrites the counter value “2”, although the counter value “1” obtained by incrementing the initialized counter value “0” by one is supposed to be rewritten, thus degrading the matching.
Such mismatching of stored data among the plurality of storage units results from the fact that the data processor for independently performing processing for the storage units cannot perform real-time processing. Therefore, when the stored data are to be processed in parallel in almost overlapping time periods by a plurality of factors, the problem of mismatching cannot be avoided.
Conventionally, to maintain matching of stored data, two or more data processors sequentially perform write processing in the corresponding storage units such that the processing periods of the data processor do not overlap. When a certain data processor is performing a processing operation including a write processing operation in the storage unit in the same processing block, and another independent data processor is to perform a processing operation including a write processing operation in a storage unit in a self processing block, less urgent processing operation must wait until more urgent processing operation has ended.
More specifically, assume that the second data processor for incrementing the counter by one and the first data processor for initializing the counter value to “0” are to perform processing of table data corresponding to the same index in overlapping periods. Even when the data processor has already started a series of processing operations from counter value load processing to counter value rewrite processing in the counter, processing operations performed by the second data processor are canceled when the first data processor having a high urgency level generates a request for loading the same index. After the counter value is initialized to “0” by the first data processor, the second data processor loads the counter value again, increments the counter value by one, and rewrites the counter value “1”.
Two conventional techniques are used to ensure matching of stored data. One is called an updating scheme. When data is written in a particular storage unit that has copied data, data in all the remaining storage units that have copied data and the storage unit with the original data are updated with the rewritten data.
The other technique is called an invalid scheme. When data is written in a particular storage unit that has the copied data, all the remaining storage units and the storage unit with the original data are notified of the address data of this storage area. Using this technique, the system indicates that the data which has already been written in the storage area at the address is not the latest data. Thus, this invalidates the data in the remaining storage units.
In the updating scheme, when one data processor has written data in the storage area of a storage unit in the same processing block, other data processor which are going to write data in the same storage area cancel their processing operations. Processing in the storage unit in the self processing block must be uselessly performed later again from the beginning.
In the invalid scheme as well, if data stored in the storage unit is subjected to a write processing operation or a reference is invalidated, data in the storage area must be read again to perform a processing operation.
In both the above schema, write processing in the same storage area must be sequentially performed.
Conventionally, to protect matching of stored data, when two or more data processor are to write data in the same storage area, processing of each data processor must be sequentially performed.
However, when data stored in the same storage area is to be
Fujisawa Toshio
Hasegawa Jun
Okada Masahiro
Saito Toshitada
Hogan & Hartson L.L.P.
Kabushiki Kaisha Toshiba
Peikari B. James
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