Formation of silicided contact by ion implantation

Details Formation of silicided contact by ion implantation Formation of silicided contact by ion implantation

1996-02-05

2002-06-18

Nguyen, Ha Tran (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S660000, C438S664000, C438S668000, C438S672000, C438S675000, C438S692000, C438S745000, C438S756000

Reexamination Certificate

active

06406998

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to methods of forming electrical contacts on silicon substrates of in-process integrated circuit wafers. More particularly, the present invention is directed to a method of forming an electrical contact including a diffusion barrier formed by metal ion implantation, the electrical contact being formed on a silicon substrate of an in-process integrated circuit wafer.
2. The Relevant Technology
Recent advances in computer technology and in electronics in general are attributable to a great degree to the progress achieved by the integrated circuit industry in electronic circuit integration and miniaturization. This progress has resulted in increasingly compact and efficient semiconductor devices, attended by an increase in the complexity and number of such devices aggregated on a single integrated circuit wafer. The smaller and more complex devices, including resistors, capacitors, diodes, and transistors, have been achieved, in part, by reducing device sizes and spacing and by reducing the junction depth of active regions formed on the silicon substrate of integrated circuit wafers. The smaller and more complex devices have also been achieved by stacking the devices at various levels on the wafer.
Among the features which are being reduced in size are the electrical contacts through which electrical communication is made between discrete semiconductor devices on the varying levels of the wafer. In order to continue in the process of reducing integrated circuit size, however, new methods of forming electrical contacts which overcome certain problems existing in the art are required.
As an example of the problems currently encountered in forming electrical contacts electrical contacts have historically been formed from aluminum or aluminum alloy metallization. Aluminum, however, presents the problem of spiking. Spiking results in the dissolution of silicon from active regions of the semiconductor devices into the aluminum metallization and the dissolution of aluminum into the active regions.
Electrical contacts have more recently been metallized with tungsten with the formation of what is known as a “tungsten plug.” The tungsten plug formation process does not incur spiking, but has proven problematic for other reasons, however, and these problems are heightened by the continuous miniaturization of the integrated circuit and the modern “stacked” construction of such circuits.
The tungsten plug is typically deposited by chemical vapor deposition (CVD) in an atmosphere of fluorine, which attacks silicon, creating “worm holes” into the active region. Worm holes formed from this reaction can extend completely through the active region, thereby shorting it out and causing the device to fail. As a further problem associated with the tungsten plug structure of the prior art, the tungsten metallization complicates the electrical contact formation process because it does not adhere well directly to silicon or oxide.
In order to eliminate the problems associated with the reaction between the silicon substrate and the metallization material, prior art methods have typically employed a diffusion barrier structure that is provided between the metallization material and the active region. The diffusion barrier prevents the inter diffusion of silicon of the active region and aluminum of the metallization material. It also provides a surface to which the tungsten will adhere and prevents fluorine from diffusing into the active region.
Prior art
FIGS. 1 through 4
of the accompanying drawings depict one conventional method known in the art of forming contact structures having a diffusion barrier. As shown in
FIG. 1
, a contact opening
16
is first etched through an insulating layer
14
overlying an active region
12
on a silicon substrate
10
. Active region
12
typically comprises a doped silicon region such as a source or a drain of a MOS transistor. Insulating layer
14
typically comprises a passivation layer of intentionally formed silicon dioxide or borophosphosilicate glass (BPSG). Contact opening
16
provides a route for electrical communication for active region
12
through the surface of insulating layer
14
. As shown in
FIG. 2
, a titanium layer
20
is sputtered over contact opening
16
in a further step, and coats the exposed surface of active region
12
.
A high temperature anneal step is then conducted in an atmosphere of predominantly nitrogen gas (N
2
). Titanium layer
20
reacts with the silicon of active region
12
during the anneal and is transformed into a dual layer. In forming the new dual layer, the lower portion of titanium layer
20
overlying active region
12
reacts with a portion of the silicon in active region
12
to form a titanium silicide (TiSi
x
) region
22
. Concurrently, the upper portion of titanium layer
20
reacts with the nitrogen gas to form a titanium nitride (TiN
x
) layer
24
. The resulting structure is shown in FIG.
3
. Titanium silicide layer
22
provides a conductive interface at the surface of active region
12
. Titanium nitride layer
24
formed above titanium silicide layer
22
acts as a diffusion barrier to the interdiffusion of tungsten and silicon, or to the interdiffusion of aluminum and silicon, as mentioned above.
Titanium nitride layer
24
can also be formed with chemical vapor deposition. A typical chemical vapor deposition process comprises the use of a precursor such as a metal organic or a halide, which is thermally decomposed, reacted with a gas such as NH
3
, or plasma-assist deposited.
The next step, shown in
FIG. 4
, is the deposition of the metallization layer. In tungsten plug formation, metallization is achieved by the chemical vapor deposition of tungsten to form metallization layer
25
. Titanium nitride layer
24
helps improve the adhesion between the walls of the opening and the tungsten metallization material. It also acts as a barrier against the diffusion of metallization layer
25
into the active region
12
, and vice-versa.
Another function of depositing titanium layer
20
in contact opening
16
is to remove native silicon dioxide (SiO
2
) which forms whenever the in-process integrated circuit wafer is exposed to oxygen, such as by way exposure to ambient air. Typical native silicon dioxide layers have a thickness of about 20 Angstroms. Such a native silicon dioxide layer
15
is shown in FIG.
1
. Native silicon dioxide layer
15
is highly insulative and can cause a high contact resistance so as to result in failure of the device being formed. Titanium layer
20
of
FIG. 2
reacts with and breaks down silicon dioxide layer
15
. In the process, a portion of titanium layer
20
is consumed. As a result, titanium layer
20
must be deposited in contact opening
16
in sufficient thickness to react with native oxide layer
15
and to also form an effective diffusion barrier.
One problem involved with the titanium silicide diffusion barrier structure is the poor step coverage provided by current titanium deposition methods.
FIG. 5
depicts the results of a typical attempt to deposit titanium with a sufficient thickness in a high aspect ratio contact opening. Note the cusping
26
or “bread loafing” of titanium on the surface of contact opening
16
. A result of cusping
26
is that contact opening
16
is eventually closed off, and cannot be completely filled. Thus, a void area, known as a “keyhole,”
28
is formed. Keyhole
28
increases the contact resistance of the electrical contact being formed, resulting in slower device performance. This is ultimately a failure condition of the integrated circuit. Also, keyhole
28
can open up during later processing steps and allow caustic materials inside, which will erode contact opening
16
. This is also a failure condition.
A further problem of prior art methods involves the migration of the integrated circuit industry toward high aspect ratios. As device dimensions continue to shrink and the contact openings become deeper and narrower, contact walls become ve

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