Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-04-28
2002-06-04
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S127000, C711S202000, C711S210000, C711S206000, C711S207000, C711S208000, C711S209000, C365S230030
Reexamination Certificate
active
06401177
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a memory system, and in particular, to a high-speed memory system suitable for a main memory unit in a general-purpose computer.
In a general-purpose computer, high-speed and large capacity has recently developed. To this end, it is increasingly required that a memory system, which is used for the computer, has the high-speed and the large capacity.
In this case, a MMU (Main Memory Unit) is arranged in the computer and is used to store data signals and programs. Further, the MMU (Main Memory Unit) generally controls accesses for the main memory from a CPU (Central Processing Unit), which performs calculation process, and further, controls an IOE (Input Output Processor).
The memory system, such as, the main memory unit, is generally divided into a plurality of banks which are independently operable. In this event, addressing is carried out for each bank.
With this structure, the banks operate in parallel. Thereby, an average access time for the memory device is largely reduced, and high operation can achieved. Such an operation is normally referred to as a memory interleaving operation or an address interleaving operation.
In the meanwhile, the memory system that has the interleaving mechanism to achieve the above-mentioned purpose is conventionally well known, as disclosed, for example, in Japanese Unexamined Patent Publications (JP-A) No. Sho. 55-32188 and Hei. 1-156852.
The former Reference discloses a restructure control system having memory modules. In such a system, memory absolute addresses are given from a processing apparatus, such as, a CPU (Central Processing Unit) or an IOP (Input Output Processor) into a memory module conversion mechanism and a memory real physical address combiner. Thereby, memory banks (blocks) can be freely restructured.
On the other hand, the latter reference discloses an interleaving control system. Such a system includes an interleaving control circuit and a bank control portion.
In the interleaving control circuit, the interleaving control can be performed via a plurality of ways between the memory banks. In the bank control portion, the memory bank to be used is designated on the basis of an output from the interleaving control circuit.
However, unit memory capacity is variable in the conventional memory device when the memory restructure is carried out so that the number of the interleaving way is degraded before and after generation of a trouble.
Further, an OS (Operating System) directly must control hardware inherent to the device, such as, the interleaving control mechanism.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a memory system which is capable of ensuring unit memory capacity before and after generation of a trouble.
It is another object of this invention to provide a memory system which is capable of preventing system-down by restructuring a memory system.
According to this invention, a memory system has a plurality of memory banks. With this structure, the memory system performs an interleaving operation between the memory banks, and restructures the memory system by dividing into a plurality of memory blocks which are independently operable. The memory system includes a first address conversion table and a second address conversion table.
The first address conversion table is referred by an Operating System and is controllable by dividing an absolute address space into each unit memory capacity.
The second address conversion table designates the memory banks and the memory blocks so that the memory banks and the memory blocks are commonly used between memory units which form the interleaving to each other based upon an output value of the first address conversion table and the number of the interleaving.
With such a structure, the unit memory capacity is invariable even when the memory restructure is carried out so that the number of the interleaving way is degraded before and after the generation of the trouble.
Further, it is unnecessary that the OS controls the interleaving control mechanism.
REFERENCES:
patent: 4737931 (1988-04-01), Ishii
patent: 5428758 (1995-06-01), Salsburg
patent: 55-32188 (1980-03-01), None
patent: 1-156852 (1989-06-01), None
Namazi Mehdi
Yoo Do Hyun
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