Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-10-17
2002-05-21
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S536000
Reexamination Certificate
active
06392251
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to test structures operable to identify open contacts on a semiconductor workpiece.
2. Description of the Related Art
Large scale integrated circuits now routinely contain millions of individual transistors and other electronic components. Most of the interconnections for the numerous individual components are provided via one or more metallization layers that serve as global interconnect levels. Each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required.
A method frequently employed to form contact structures involves a damascene process in which the substrate containing the integrated circuit is coated with a layer of dielectric material that is lithographically patterned and etched to form contacts or vias in the dielectric layer where the contact structures will be formed. Thereafter, the contact material or materials if a laminate structure is desired are deposited over the dielectric layer. The goal of the deposition process is to fill the vias as completely as possible. Finally, a planarization process is performed to remove the excess conducting material from the dielectric layer and leave only the filled vias.
Oxides of silicon are commonly used as interlevel dielectric layer materials. Where materials that exhibit relatively poor adhesion to oxides, such as tungsten, are utilized for the contacts, the deposition of an adhesion film that exhibits acceptable adhesion to both oxide and the contact material is first deposited followed by the deposition of the bulk conducting material. Thereafter, the planarization process is performed to remove the portions of the deposited conducting films overlying the interlevel dielectric layer and to leave conducting material only in the contacts.
Like many aspects of modern semiconductor fabrication, quality control in the formation of contact structures is vital to device operation and productive manufacturing yields. As the fabrication of contacts involves several sequentially performed processing steps, a number of mechanisms arise that may interfere with the successful fabrication of the contacts and lead to open contacts that do not make a complete circuit. Examples of potential process mechanisms that may lead to contact failure are legion, and includes such things as line scumming, poor contact etching, particulate contamination in contacts, and poor reticle design to name just a few.
Conventional techniques for diagnosing potential causes for contact failure do not enable the process engineer to rapidly zero in on the locations and potential causes of defective contacts. One conventional method involves the complete electrical test of an entire chip or die for electrical defects. This test involves an electrical diagnostic of the active circuit structures on a given chip and may include electrical examination of various test circuit structures that are fabricated on the die. The difficulty with this approach is not only the time consuming nature of the diagnostic test but also the potential inability to accurately: (1) identify defective contacts; and (2) the likely cause of the contact defects. In some cases a region of the die that is exhibiting electrical failure undergoes a diagnostic technique known as deprocessing. The suspect area of the die is examined in more detail, often using visual inspection of die cross-sections. Using the visual inspection as a guide, the process steps leading up to the formation of the structure in question are closely examined for possible sources of process variations or other mechanisms that lead to contact failure.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing, disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a test structure is provided that includes a substrate, a first conductor on the substrate and a second conductor on the substrate. A resistor network is coupled in parallel between the first conductor and the second conductor. The resistor network has n resistors and n contacts and a measurable resistance R
M
. Each of the n resistors has a known resistance R
k
and a known position on the substrate. Each of the n contacts is connected between one of the n resistors and the first conductor or the second conductor, whereby the location of any of the n contacts in an open state is determined from the equation:
R
M
=
1
1
R
k
+
…
1
R
n
In accordance with another aspect of the present invention, a test structure is provided that includes a substrate, a first conductor on the substrate, a second conductor on the substrate and n contacts connected in series between the first conductor and the second conductor and defining n/2 pairs of the n contacts. Each of the n contacts has a known resistance R
c
. A plurality of resistors is provided. Each of the plurality of resistors has a known resistance R
k
and a known position on the substrate and is connected in parallel with one of the n/2 pairs of n contacts. The n contacts and the plurality of resistors have a combined measurable resistance R
M
, whereby the location of any of the n contacts in an open state is determined from the equation:
R
M
=
∑
K
=
1
n
2
R
c
R
K
2
R
c
+
R
K
In accordance with another aspect of the present invention, an integrated circuit is provided that includes a substrate, a plurality of circuit devices on the substrate, a plurality of active contacts coupled to the plurality of circuit devices, and a test structure. The test structure has a first conductor on the substrate, a second conductor on the substrate, and a resistor network coupled in parallel between the first conductor and the second conductor. The resistor network has n resistors and n contacts and a measurable resistance R
M
. Each of the n resistors has a known resistance R
k
and a known position on the substrate. Each of the n contacts is connected between one of the n resistors and the first conductor or the second conductor, whereby the location of any of the n contacts in an open state is determined from the equation:
R
M
=
1
1
R
k
+
…
1
R
n
In accordance with another aspect of the present invention, an integrated circuit is provided that includes a substrate, a plurality of circuit devices on the substrate, a plurality of active contacts coupled to the plurality of circuit devices, and a test structure. The test structure has a first conductor on the substrate, a second conductor on the substrate and n contacts connected in series between the first conductor and the second conductor and defining n/2 pairs of the n contacts. Each of the n contacts has a known resistance R
c
. A plurality of resistors is provided. Each of the plurality resistors has a known resistance R
k
and a known position on the substrate and is connected in parallel with one of the n/2 pairs of n contacts. The n contacts and the plurality of resistors having a combined measurable resistance R
M
, whereby the location of any of the n contacts in an open state is determined from the equation:
R
M
=
∑
K
=
1
n
2
R
c
R
K
2
R
c
+
R
K
REFERENCES:
patent: 4347479 (1982-08-01), Cullet
patent: 5563517 (1996-10-01), Biery et al.
patent: 6007405 (1999-12-01), Mei
patent: 6080597 (2000-06-01), Moon
Stanley Wolf and Richard N. Tauber;Silicon Processing for the VLSI Era, vol. 2—Process Integration; pp. 87-110; 1990.
Cooper David
McCarthy Michael
Advanced Micro Devices , Inc.
Honeycutt Timothy M.
Ngo Ngan V.
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