Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-04-09
2002-08-27
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S162000, C438S163000, C438S164000
Reexamination Certificate
active
06440784
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor and a fabricating method thereof wherein a source/drain region and a gate electrode are formed from the same layer.
2. Discussion of Related Art
Compared to an amorphous silicon thin film transistor (hereinafter abbreviated TFT), a polycrystalline silicon TFT has a high mobility of electrons and holes and can be used as a CMOS TFT. Accordingly, a liquid crystal display (hereinafter abbreviated LCD) having polycrystalline silicon TFTs has a structure such that both a driver and a pixel array are formed on a glass substrate.
When polycrystalline silicon TFTs are used to form a driver, switching operations of the LCD at a fast frequency is possible because of the characteristics of polycrystalline silicon. However, when polycrystalline silicon TFTs are fabricated on a pixel array in an LCD, the characteristics of the image is deteriorated by the high drain current of the off-states due to the characteristics of polycrystalline silicon.
More recently, in order to reduce the off-current in a pixel array to a proper level, TFTs having a lightly doped drain (hereinafter abbreviated LDD) structure, an offset structure, or the like, have been used in the related art.
FIG. 1
shows a cross-sectional view of a TFT according to the related art. Referring to
FIG. 1
, a buffer oxidation layer
13
is formed on an insulated substrate
11
, and an active layer
15
of polycrystalline silicon is formed on the buffer oxidation layer
13
. In a predetermined portion of the active layer
15
, a gate insulating layer
17
and a gate electrode
19
are formed, wherein the channel region is in the middle of the active layer
15
and the length of the gate electrode
19
is shorter than that of the gate insulating layer
17
.
The sides of the active layer
15
extending beyond the gate electrode
19
are doped with n- or p- type impurities. The region of the active layer that also extends beyond gate insulating layer
17
becomes a source region
21
and a drain region
22
, doped heavily with impurities. The region of the active layer that extends beyond the gate electrode, but not beyond the gate insulating electrode, becomes a lightly doped region
23
that forms an LDD. The portion of the active layer that lies between the LDD regions becomes a channel region
15
.
An insulating interlayer
25
of silicon oxide or silicon nitride is formed over the entire surface of the above structure. First contact holes
27
exposing the source and drain regions
21
and
22
are formed in the insulating interlayer
25
. Source and drain electrodes
29
and
30
, connected electrically to the source and drain regions
21
and
22
, are then formed in the first contact holes
27
.
A passivation layer
31
consisting of silicon oxide is formed on the insulating interlayer
25
to cover the source and drain electrodes
29
and
30
. A second contact hole
33
exposing the drain electrode
30
is then formed in the passivation layer
31
. A pixel electrode
35
is connected electrically to the exposed drain electrode
22
through the second contact hole
33
formed in the passivation layer
31
. In this case, the pixel electrode
35
is made of a substance which is transparent and electrically conductive such as indium-tin oxide (hereinafter abbreviated ITO), tin oxide (hereinafter abbreviated TO), or the like.
FIGS. 2A
to
2
E show cross-sectional views of the fabrication of the TFT according to a related art. Referring to
FIG. 2A
, a buffer oxidation layer is formed on a transparent insulated substrate
11
, such as glass or and the like, by depositing silicon oxide by chemical vapor deposition (hereinafter abbreviated CVD). An active layer
15
is formed by deposition of amorphous silicon on the buffer oxidation layer
13
, followed by dehydration and crystallization. The buffer oxidation layer
13
of this embodiment is then annealed by a laser, thereby preventing the active layer
15
from being penetrated by the impurities in the insulated substrate
11
. Next, the active layer
15
is patterned by photolithography so that the photoresist remains on a predetermined portion of the buffer oxidation layer
13
.
In the above step, the active layer
15
may be formed by depositing polycrystalline silicon at low temperature instead of by deposition, dehydration and crystallization of amorphous silicon.
Referring to
FIG. 2B
, an insulating substance such as silicon oxide, silicon nitride, or the like, is deposited on the buffer oxidation layer
13
by CVD to cover the active layer
15
. Next, metal such as aluminum (Al) or molybdenum (Mo), or the like, is deposited on the insulating substance.
A photoresist pattern
20
remaining on a portion corresponding to the middle part of the active layer
15
is defined by coating the metal with photoresist and by exposing and developing the photoresist. Next, a gate electrode
19
and a gate insulating layer
17
are formed by patterning the metal and the insulating substance using the photoresist pattern as a mask.
In preferred embodiments, the gate electrode
19
and the gate insulating layer
17
are formed by anisotropically etching the metal and the insulating substance to expose the active layer
15
and by selectively overetching the metal to expose both side surfaces of the gate insulating layer
17
. Thus the length of the gate electrode
19
is shorter than that of the gate insulating layer
17
.
Referring to
FIG. 2C
, the photoresist pattern
20
is removed, and source and drain regions
21
and
22
and a lightly doped region
23
are formed by doping the active layer
15
with n-type impurities such as phosphorus (P), arsenic (As), or the like, using of the gate electrode
19
as a mask, with high dose and low energy ion implantation and with low dose and high energy ion implantation, respectively. In this case, the source and drain regions
21
and
22
are formed on exposed portions of the active layer
15
that extend beyond the gate insulating layer
17
, while the lightly doped region
23
is formed where the gate insulating layer
17
overlaps the active layer
15
.
Referring to
FIG. 2D
, an insulating interlayer
25
is formed by depositing insulating substance, such as silicon oxide, silicon nitride, or the like, on the entire surface of the above structure. Next, first contact holes
27
exposing the source and drain regions
21
and
22
are formed by removing predetermined portions of the insulating interlayer
25
by conventional photolithography and etching.
Metal, such as Al, or the like, is deposited on the insulating interlayer
25
to contact the source and drain regions
21
and
22
by filling up the first contact holes
27
. Source and drain electrodes
29
and
30
, connected electrically to the source and drain regions
21
and
22
, are formed by patterning the metal to remain inside the first contact holes
27
by photolithography and etching.
Referring to
FIG. 2E
, a passivation layer
31
is formed on the insulating interlayer
25
by CVD of an insulating substance such as silicon oxide, silicon nitride, or the like, to cover the source and drain electrodes
29
and
30
. Then, a second contact hole
33
, exposing the drain electrode
30
, is formed by removing a predetermined portion of the passivation layer
31
by photolithography and etching.
Next, a pixel electrode
35
, connected electrically to the exposed drain electrode
22
through the second contact hole
33
, is formed on the passivation layer
31
by depositing and patterning a substance which is transparent and electrically conductive. For example, a substance such as ITO or the like, may be used.
The TFT according to the related art has a top-gate structure because (1) the gate electrode is formed to expose both sides of the gate insulating layer, (2) the source and drain regions are formed in the exposed portions of the active layer with no gate insulating layer and (3) the lightly doped regions are formed in another portion overlapped with the gate insu
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Schillinger Laura M
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