Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-16
2002-04-23
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S643000, C438S692000
Reexamination Certificate
active
06376376
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of preventing dishing during copper damascene formation in the manufacture of integrated circuits.
(2) Description of the Prior Art
Currently, the copper damascene formation process makes use of three chemical mechanical polish (CMP) steps with different slurries. These steps are the bulk copper CMP step, barrier removal step, and buffing step. This existing process is complex and dishing of the copper line usually occurs during the barrier removal step. The barrier is usually tantalum nitride (TaN) which is much harder than the copper and chemically very stable. The dishing in the copper line will have an impact on the metallization resistance that causes RC delay to vary.
Co-pending U.S. patent application Ser. No. 09/893,080 to W. X. Bin et al filed on Jun. 28, 2001 discloses a SiN capping layer over oxide for protection of the oxide layer during copper or tungsten CMP. U.S. Pat. No. 6,071,809 to Zhao teaches a SiN/SiO
2
dual hard mask layer as a polish stop layer for copper CMP. U.S. Pat. No. 6,001,730 to Farkas et al discloses a two-step CMP of copper with a TaN barrier layer. Co-pending U.S. patent application Ser. No. 09/425,310 to F. Chen et al, filed on Oct. 25, 1999 discloses a sacrificial high polishing rate layer over an oxide layer and under a barrier layer and tungsten layer in order to prevent dishing during CMP. Co-pending U.S. patent application Ser. No. 09/110,419 to Sudipto R. Roy filed on Jul. 6, 1998 discloses a sacrificial or semi-sacrificial titanium nitride layer deposited over the oxide to protect the oxide and to act as an endpoint detector. Polishing rates of the tungsten and the titanium nitride are comparable, resulting in dishing. U.S. Pat. No. 5,578,523 to Fiordalice et al teaches the use of a polish assisting layer over a dielectric layer and under a metal layer deposited within a trench. The polish assisting layer and the metal layer are polished at close to the same rate in the final stages of polishing, thus preventing dishing. U.S. Pat. No. 5,798,302 to Hudson et al teaches a low friction layer under a metal layer wherein the polishing rate of the low friction layer is much lower than that of the metal layer causing the CMP process to stop at the top surface of the low friction layer. U.S. Pat. No. 5,886,410 to Chiang et al discloses a hard mask over a polymer through which a trench is etched and filled with tungsten. The tungsten is polished with a higher selectivity to tungsten than to the underlying hard mask. U.S. Pat. No. 5,854,140 to Jaso et al teaches a metal stop layer under an aluminum trench filling layer. The aluminum is polished to the stop layer, resulting in dishing. Then the stop layer is removed with a very high selectivity to the stop layer over the aluminum layer so that the resulting aluminum is substantially planar. U.S. Pat. No. 5,776,833 to Chen et al teaches a titanium nitride layer under a tungsten plug layer. CMP stops at the titanium nitride layer. The titanium nitride layer is then removes by etching rather than by polishing resulting in a protruding tungsten plug. U.S. Pat. No. 5,356,513 to Burke et al discloses alternating layers of soft polishing material and hard polish stops to provide tungsten plugs having a substantially planar surface. U.S. Pat. No. 6,100,197 to Hasegawa et al teaches a copper CMP process. U.S. Pat. No. 6,048,796 to Wang et al discloses a silicon nitride layer over oxide for prevention of particles penetration into the oxide layer during CMP. U.S. Pat. No. 6,096,632 to Drynan teaches a tungsten CMP process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of plug metallization including CMP.
Another object of the invention is to provide a method of copper damascene metallization including CMP.
Yet another object is to provide a method of copper damascene metallization in which copper dishing is prevented.
Yet another object is to provide a method of copper damascene metallization in which fewer CMP steps are required.
A still further object of the invention is to provide a method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line.
In accordance with the objects of this invention a new method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line after CMP is achieved. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. A polish stop layer is deposited overlying the insulating layer. An oxide layer is deposited overlying the polish stop layer. An opening is etched through the oxide layer, the polish stop layer, and the insulating layer to one of the semiconductor device structures. A barrier metal layer is deposited over the surface of the oxide layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and the barrier metal layer not within the opening are polished away wherein the barrier metal layer polishes more slowly than the copper layer whereby dishing of the copper layer occurs. Thereafter, the oxide layer is polished away stopping at the polish stop layer wherein the oxide layer polishes more quickly than the copper layer whereby the dishing of the copper layer is removed and whereby a hump is formed on the copper layer after the oxide layer is completely polished away. The copper layer is overpolished to remove the hump to complete copper damascene metallization in the fabrication of an integrated circuit.
REFERENCES:
patent: 5356513 (1994-10-01), Burke et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5776833 (1998-07-01), Chen et al.
patent: 5798302 (1998-08-01), Hudson et al.
patent: 5854140 (1998-12-01), Jaso et al.
patent: 5886410 (1999-03-01), Chiang et al.
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6004188 (1999-12-01), Roy
patent: 6040243 (2000-03-01), Li et al.
patent: 6048796 (2000-04-01), Wang et al.
patent: 6071809 (2000-06-01), Zhao
patent: 6096632 (2000-08-01), Drynan
patent: 6100197 (2000-08-01), Hasegawa
patent: 6150269 (2000-11-01), Roy
patent: 6184138 (2001-02-01), Ho et al.
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patent: 6225223 (2001-05-01), Liu et al.
patent: 6258711 (2001-07-01), Laursen
Chen Feng
Goh Wang Ling
Lim Victor Seng Keong
Chartered Semiconductor Manufacturing Ltd.
Nguyen Tuan H.
Pike Rosemary L. S.
Saile George O.
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