Process for forming gate conductors

Details Process for forming gate conductors Process for forming gate conductors

2000-06-20

2002-05-21

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S585000, C438S595000

Reexamination Certificate

active

06391753

ABSTRACT:

FIELD OF INVENTION
The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with small and/or densely packed gate conductors.
BACKGROUND OF THE INVENTION
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) circuits. Over the last two decades, reduction in the size of CMOS transistors has been a principal focus of the microelectronics industry.
Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally either bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices. Most integrated circuits are fabricated in a CMOS process on a bulk semiconductor substrate.
In bulk semiconductor-type devices, transistors, such as, MOSFETs, are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of depletion layer below the inversion channel) must be scaled down to achieve superior short-channel performance.
Conventional SOI-type devices include an insulative substrate attached to a thin-film semiconductor substrate that contains transistors similar to the MOSFETs described with respect to bulk semiconductor-type devices. The insulative substrate generally includes a buried insulative layer above a lower semiconductor base layer. The transistors on the insulative substrate have superior performance characteristics due to the thin-film nature of the semiconductor substrate and the insulative properties of the buried insulative layer. In a fully depleted (FD) MOSFET, the body thickness is so small that the depletion region has a limited vertical extension, thereby eliminating link effect and lowering hot carrier degradation. The superior performance of SOI devices is manifested in superior short-channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current.
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. Generally, the gate conductor can be a metal, a polysilicon, or polysilicon/germanium (Si
x
Ge
(1−x)
) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
Generally, it is desirous to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirous to reduce the size of integrated circuit structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc. For example, manufacturing a transistor having a reduced gate length (a reduced width of the gate conductor) can have significant benefits. Gate conductors with reduced widths can be formed more closely together, thereby increasing the transistor density on the IC. Further, gate conductors with reduced widths allow smaller transistors to be designed, thereby increasing speed and reducing power requirements for the transistors.
Heretofore, lithographic tools are utilized to form transistors and other structures on the integrated circuit. For example, lithographic tools can be utilized to define gate conductors, conductive lines, vias, doped regions, and other structures associated with an integrated circuit. Most conventional lithographic fabrication processes have only been able to define structures or regions having a dimension of 100 nm or greater.
In one type of conventional lithographic fabrication process, a photoresist mask is coated over a substrate or a layer above the substrate. The photoresist mask is lithographically patterned by providing electromagnetic radiation, such as, ultraviolet light, through an overlay mask. The portions of the photoresist mask exposed to the electromagnetic radiation react (e.g. are cured). The uncured portions of the photoresist mask are removed, thereby transposing and the pattern associated with the overlay to the photoresist mask. The patterned photoresist mask is utilized to etch other mask layers or structures. The etched mask layer and structures, in turn, can be used to define doping regions, other structures, vias, lines, etc.
As the dimensions of structures or features on the integrated circuit reach levels below 100 nm or 50 nm, lithographic techniques are unable to precisely and accurately define the feature. For example, as described above, reduction of the width of the gate conductor (the gate length) associated with a transistor has significant beneficial effects. Future designs of transistors may require that the gate conductor have a width of less than 50 nanometers.
Thus, there is a need for an integrated circuit or electronic device that includes smaller, more densely disposed gate conductors. Further still, there is a need for a ULSI circuit which does not utilize conventional lithographic techniques to define gate conductors. Even further still, there is a need for a non-lithographic approach for defining gates having at least one topographic dimension less than 100 nanometers and less than 50 nanometers (e.g., 20-50 nm). Yet further still, there is a need for an SOI integrated circuit with transistors having gate lengths of about 20 to 50 nm.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of manufacturing an integrated circuit including transistors. The transistors include a first transistor having a gate structure disposed on a film. The method includes removing portions of a mask layer above a conductive layer above the film to form a mask feature, providing and removing portions of an oxide material above the mask feature in the conductive layer to leave a spacer on at least one sidewall of the mask feature. The method also includes removing the mask layer, and etching the conductive layer in accordance with the spacer, thereby forming the gate structure.
Another exemplary embodiment relates to a process of forming a gate conductor. The gate conductor has a dimension less than one lithographic feature. The process includes providing a conductive layer above a top surface of a substrate, providing a mask layer above the conductive layer, patterning the mask layer to have a sidewall, providing an insulative spacer on the sidewall of the mask layer, removing the mask layer, and etching the conductive layer in accordance with the insulative spacer. Etching the conductive layer in accordance with the insulative spacer forms the gate conductor.
Yet another embodiment relates to a method of manufacturing structures on a ultra-large scale integrated circuit. The gate structures have at least one dimension less than 50 nm. The method includes steps of depositing a mask layer over a top surface of a conductive layer above a substrate, lithographically patterning the mask layer to have a plurality of islands, providing spacers on sidewalls of the islands, removing the islands, and removing portions of the conductive layer. The islands have a dimension at least 50 nm wide. The portions of the conductive layer are removed in accordance with the spacers to form the gate structures.


REFERENCES:
patent: 5889302 (1999-03

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