Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-10-16
2002-05-07
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S724000
Reexamination Certificate
active
06383943
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention generally relates to an interconnection process used in semiconductor manufacturing and, more particularly, to a method for improving the reliability of connections between different layers of metal or conducting material in the fabrication of integrated circuits.
(2) Description of Prior Art
To improve the device speed of logic on sub-quarter micron semiconductor circuits, copper has gained popularity as an interconnect material. This takes advantage of the copper's low electrical resistivity and superior resistance to electro-migration. In circuit employing multi-level interconnection, vias are used to connect the different conducting levels. The vias must provide reliable, low resistance interconnection between the conducting levels.
Referring now to
FIG. 1
, a typical via process is depicted in cross-section. A substrate layer
10
is provided. The substrate layer
10
may contain underlying layers, devices, junctions, and other features covered by an insulating layer formed prior to deposition and patterning of the first conductive layer
12
. A silicon nitride (SiN) etch stop layer
14
is provided overlying the first conductive layer
12
. An inter-metal dielectric (IMD) layer
16
overlies the entire surface. An anisotropic etch is performed leaving via holes
18
in the IMD layer
16
. Referring now to
FIG. 2
, a second etch step is performed to remove the etch stop layer
14
not protected by the IMD) layer thereby extending the via holes
18
to the first conductive layer
12
. Because of the etch selectivity of the SiN etch stop layer
14
over the IMD layer
16
, a notch profile
19
results as shown at the bottom of the via hole
18
as shown in FIG.
2
.
Referring now to
FIG. 3
, a conductive glue layer
20
composed of tantalum nitride (TaN) is applied to the surface of the wafer, lining the via holes
18
. Thereafter a second conductive layer
22
such as copper is deposited on the surface of the wafer, filling the via holes
18
. The notch at the base of the via hole
18
causes discontinuous deposition of the conductive glue layer
20
and may result in an open or poor electrical connection between the first conductive layer
12
and the second conductive layer
22
. As shown in
FIG. 4
, chemical mechanical polishing (CMP) is used to planarize the surface exposing the top of the IMD layer
16
and completing the via structure.
The prior art shown above illustrates the difficulty in etching vias. Incomplete clearing of etch by-product residue at the bottom of narrow trenches and the formation of the notch profile may result in poor or open connections between the via metal and the first conductive layer. These problems may be exaggerated by the fact that etch rates increase in areas where via density is higher.
Other approaches improving interconnections exist. U.S. Patent No. 6,010,962 to Lui et al. teaches a method where a glue layer is deposited in a via hole followed by a thin seed copper layer. The via hole is filled with photoresist to keep contaminants from entering during CMP planarization. After CMP the photoresist is removed by dry ashing and. electroless plating is incorporated to fill the via hole with copper. U.S. Patent No. 6,054,398 to Pramanick teaches a method for using low-K fluorinated dielectrics in interconnection. Tantalum (Ta) is first conformally deposited in a carbon or silicon ambient to form a carbide or silicide along the sidewalls of the via hole. This suppresses the reaction between the Ta and the low-K fluorinated dielectrics. Thereafter the glue layer of Ta or tantalum nitride (TaN) can be applied to line the via hole which is then filled with copper. U.S. Pat. No. 5,654,232 to Gardner teaches a method using silicon nitride (SiN) as a via hole liner. Copper is sputtered onto the surface filling the via hole. While maintaining the vacuum from sputtering, the copper is reflowed and oxidation of the copper surface is avoided. U.S. Pat. No. 4,519,872 to Anderson, Jr. et al. teaches a method using polymers to create lift-off structures in the formation of multiple level interconnections. U.S. Patent No. 5,512,514 to Lee teaches a method of using pillars in the creation of vias in multilevel metalization. U.S. Patent No. 5,691,238 to Avanzino et al teaches a method using a dual and triple damascene process whereby pillars are created to complete interlevel connection. U.S. Patent No. 5,693,568 to Liu et al. teaches a method using two conductive layers with a conductive etch stop layer between them. First all three layers are selectively etched to form the pattern for the lower conductors. The openings between the conductors are then filled with a dielectric. The upper conductive layer is then patterned and etched to form the interlevel vias. The openings in the upper conductive layer are then filled and the wafer surface covered with dielectric. The surface is planarized exposing the tops of the upper conductive layer. This process is repeated to form multiple levels of interconnection. U.S. Pat. No. 5,846,876 to Bandyapadhyay et al. teaches a method using multiple conductive levels to reduce conductor spacing while avoiding problems of increased capacitance.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a process that allows the formation of reliable interlevel conductor connection.
Another object of the present invention is to provide a process that allows the formation of reliable interlevel conductor connection by eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom of the via resulting from the notch in the silicon nitride etch stop layer.
These objects are achieved by using a process where a substrate layer is provided containing underlying layers, devices, junctions, and other features covered by an insulating layer. First conductive layer traces are patterned and a silicon nitride (SiN) etch stop layer is provided overlying the first conductive layer. An inter-metal dielectric (IMD) layer overlies the entire surface. An anisotropic etch is performed leaving via holes in the IMD layer followed by a second anisotropic etch step to remove the etch stop layer not protected by the ID layer. This results in the formation of the notch profile described in the prior art. An ammonia (NH
3
), nitrogen/hydrogen (N
2
/H
2
) or N
2
plasma treatment is performed to nitridize the dielectric surfaces. A wet polymer process cleaning is performed which removes the nitridized surface of the dielectric layer thereby eliminating the notch. The process then continues as described in the prior art.
REFERENCES:
patent: 4519872 (1985-05-01), Anderson, Jr. et al.
patent: 5512514 (1996-04-01), Lee
patent: 5654232 (1997-08-01), Gardner
patent: 5691238 (1997-11-01), Avanzino et al.
patent: 5693568 (1997-12-01), Liu et al.
patent: 5846876 (1998-12-01), Bandyopadhyay et al.
patent: 5998253 (1999-12-01), Loh et al.
patent: 6010962 (2000-01-01), Liu et al.
patent: 6054398 (2000-04-01), Pramanick
patent: 6228701 (2001-05-01), Dehm et al.
Chen Chao-Cheng
Lin Bor-Shyang
Liu Jen-Cheng
Shieh Jyu-Horng
Tsai Chia-Shiung
Ackerman Stephen B.
Chen Kin-Chan
Pike Rosemary L.S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Process for improving copper fill integrity does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for improving copper fill integrity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for improving copper fill integrity will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2895590