Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-04-09
2002-09-03
Tran, M. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06445607
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a method for operating an integrated memory having a memory cell array which has column lines and row lines. The memory has memory cells which each have a selection transistor and a storage capacitor with a ferroelectric storage effect, and a plate line, which is connected to one of the column lines via a series circuit containing the selection transistor and the storage capacitor of respective memory cells, in which control terminals of the selection transistors of the memory cells are connected to a respective one of the row lines.
Integrated memories having what are referred to as FeRAM memory cells, which have a ferroelectric storage effect, are often constructed in a similar manner to dynamic random access memories (DRAMs), for example. In that case, the memory cells are usually combined in a matrix-type memory cell array to form units of column lines and row lines. The memory cells each contain a selection transistor and a storage capacitor. In this case, the control terminals of the respective selection transistors of the memory cells are connected to a respective one of the row lines. The column lines are generally connected to a sense amplifier, at which an evaluated and amplified data signal can be picked off.
In memory cells with a ferroelectric storage effect, data signals are stored, as is known, in the form of different polarization states of the material in a storage capacitor of the memory cell. During operation of the memory, the memory cells generally have a capacitive behavior. Integrated memories having memory cells of this type are known for example as “FeRAMS”. In this case, the memory cells or their series circuit containing the selection transistor and the storage capacitor are usually connected between one of the column lines and a plate line, also referred to as “plate”. The plate line is usually connected to a driver circuit through which the plate line is present at a predetermined potential.
During operation of the integrated memory, the column lines and the plate lines of the memory each have active or inactive operating modes. In an active operating mode in which, for example, the content of one of the memory cells is read out, the corresponding selection transistor is activated and the corresponding column line is connected to a sense amplifier. The plate line is present at a predetermined potential. Therefore, there is a differential voltage present between the plate line and the corresponding column line. In an inactive operating mode, the corresponding column lines and the plate lines are generally connected to a terminal for a common supply potential.
During an access cycle, a differential voltage between the respective column line and the plate line is likewise present, across the respective source-drain paths of unactivated selection transistors of unselected memory cells. This source-drain voltage can cause a “leakage current” in the respective selection transistor. During each access cycle, the associated storage capacitors of unselected memory cells are charged and/or discharged by certain quantities of charge. As a result, the voltage across the respective storage capacitor can change during each access cycle.
In a ferroelectric memory, the information in a memory cell is stored by the amount of remnant polarization, no voltage being present between the terminals of the storage capacitor. The read-out of the information is achieved by momentarily applying a voltage to the terminals of the capacitor. As a result of the above-described charging or discharging of the storage capacitor on account of a leakage current and as a result of the associated change in potential across the capacitor, the information stored in the memory cell can be attenuated or destroyed over time or after a plurality of access cycles.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for operating an integrated memory which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which an attenuation or destruction of the information stored in a memory cell, which is caused by source-drain leakage currents of selection transistors, is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, an operating method which includes providing an integrated memory having a memory cell array of memory cells, column lines, and row lines. The memory cells have selection transistors and storage capacitors with a ferroelectric storage effect. The integrated memory further has a plate line connected to one of the column lines through a series circuit containing a selection transistor and a storage capacitor of each of the memory cells. The selection transistors have control terminals each connected to a respective one of the row lines, and the memory cells can be accessed in an access cycle. Prior to an access, a column line and the plate line connected. to a memory cell to be selected are set to an initial potential. During the access, a row line connected to the memory cell to be selected is activated, with a result that the selection transistor of the memory cell is switched on. A further potential is applied to the plate line, the further potential being different from the initial potential of the column line. A potential present on the column line at a first instant is evaluated and amplified. The initial potential is applied to the plate line at a second instant. The initial potential is applied to the column line at a third instant. The first instant, the second instant and the third instant are chosen such that, in the access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by an equivalent amount.
The ferroelectric memory is operated in a “pulsed plate concept”, in which the plate line has pulsed signals. In order to avoid a loss of information in unselected memory cells, the time sequence of an access cycle is controlled in a suitable manner. If, for this purpose, the first instant, the second instant and the third instant are chosen such that the selected storage capacitor is in each case charged and discharged by the same amount, then this effect is also achieved in the case of unselected storage capacitors which are charged and/or discharged on account of source-drain leakage currents. If an access cycle is temporally controlled by the method according to the invention, then a DC voltage component of the differential voltage between the plate line and the relevant column line tends toward zero. The differential voltage now contains only a pure AC voltage component, i.e. a connected storage capacitor is in each case charged and discharged again by the same amount during an access cycle.
An existing DC voltage component can be calculated mathematically by integration of the differential voltage between the plate line and the corresponding column line over time. If this integral has a value which tends toward zero at the end of the access cycle, then the differential voltage has no DC voltage component.
By way of example, the shortest possible period of time from a technical standpoint is chosen as the period of time between the first instant and the third instant. In other words, the control of the temporal sequence during a memory access is set only by a corresponding choice of the first instant.
In accordance with an added mode of the invention, there is the step of setting the initial potential to be a reference-ground potential of the integrated memory.
In accordance with another mode of the invention, the access to the memory cell to be selected is a read access for reading out a data signal of the memory cell.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for operating an integrated memory, it is nevertheless not intended to be limited to the details shown,
Esterl Robert
Hönigschmid Heinz
Kandolf Helmut
Röhr Thomas
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Tran M.
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