Methods of reading and writing data from/ on semiconductor...

Details Methods of reading and writing data from/ on semiconductor... Methods of reading and writing data from/ on semiconductor...

2001-03-08

2002-08-20

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06438021

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory device, in which a ferroelectric capacitor is connected in series to the gate electrode of a field effect transistor (FET).
A ferroelectric FET (FeFET) is a nonvolatile memory device including a ferroelectric and an FET in combination. An FeFET may have any of various types of device structures, which can be roughly classified into the categories of: MFS FeFETs; MFIS FeFETs and MFMIS FeFETs. As used herein, “MFS”, “MFIS” and “MFMIS” are the acronyms standing for metal-ferroelectric-semiconductor, metal-ferroelectric-insulator-semiconductor and metal-ferroelectric-metal-insulator-semiconductor, respectively.
FIG. 9
is a cross-sectional view illustrating a structure for an MFMIS FeFET for use in the present invention. As shown in
FIG. 9
, the MFMIS FeFET has a multilayer structure consisting of dielectric
34
, floating gate electrode
35
, ferroelectric
36
and control electrode
37
that have been stacked in this order on a p-type silicon (Si) substrate
31
. In the p-type Si substrate
31
, a pair of n-type heavily doped regions
32
and
33
has been defined as source and drain electrodes, respectively. In this structure, a ferroelectric capacitor has been formed on the floating gate electrode
35
of an FET, and the electrode
35
is used in common for the ferroelectric capacitor and FET. A structure, in which the electrode of a ferroelectric capacitor is connected to the gate electrode of an FET through a line, is also a type of MFMIS FeFET.
Next, it will be described how an MFMIS FeFET with such a structure operates as a nonvolatile memory device.
When a voltage Vg applied to the control electrode has its polarity inverted into a positive or negative value, the direction of polarization in the ferroelectric reverses. In the following description, to apply a positive voltage Vg to the control electrode will mean to write data “1” on the ferroelectric, while to apply a negative voltage Vg to the control electrode will mean to write data “0” on the ferroelectric.
Even after the voltage applied has been removed from the control electrode to allow the electrode to be floating, the polarization is left in the ferroelectric, which is called “remanent polarization”. To read data out, a voltage is applied between the source/drain electrodes while allowing the control electrode to be floating. In this state, the potential level at the control electrode is believed to be close to the ground level, because there is a leakage current flowing due to the existence of resistive components and because there is also a coupling capacitance created between the electrode and a line connected thereto. On the other hand, the potential level at the floating gate electrode of the FET may be either positive or negative depending on the direction of remanent polarization existing in the ferroelectric capacitor. If the potential level at the floating gate electrode is positive and higher than the threshold voltage of the FET, then the FET turns ON, thus allowing a current to flow between the source and drain regions. Alternatively, if the potential level at the floating gate electrode is negative, then the FET turns OFF and no source-drain current flows. By comparing a sourcedrain current value Ids with a predetermined reference current value Iref and defining Ids>Iref and Ids<Iref as representing data “1” and data “0”, respectively, the data written can be read out accurately.
By way of an illustrative example, a simulation will be run on the operation of an MFMIS FeFET that uses strontium bismuth tantalate (SrBi
2
Ta
2
O
9
) as its ferroelectric and silicon dioxide (SiO
2
) as its dielectric, respectively.
FIG. 10
illustrates an equivalent circuit for the FeFET.
Now it will be described with reference to
FIG. 10
how the MFMIS FeFET operates. In
FIG. 10
, the ferroelectric capacitor, FET and control, source and drain electrodes are identified by the reference numerals
41
,
42
,
43
,
44
and
45
, respectively.
The parameters are set as follows. Suppose the SrBi
2
Ta
2
O
9
has a thickness of 200 nm, a dielectric constant of 300 and a coercive voltage of 0.8 V, while the SiO
2
has a thickness of 3.5 nm and a dielectric constant of 3.9. The f erroelectric capacitor, which is the MFM section of the MFMIS structure, has a polarization Pf and an interelectrode voltage Vf and is supplied with a voltage Vg at the control electrode thereof. As for the FET, or the MIS section of the MFMIS structure, a charge Qi has been stored in the gate, voltages Vd, Vi and Vs (where Vs=0 V) are applied to the drain, floating gate and source electrodes, respectively, and the potential level at the substrate is 0 V. And when the FET alone is operated by electrically disconnecting the ferroelectric capacitor from the FET, the threshold voltage vti of the FET is supposed to be 0.5 V.
A memory cell like this meets the following two Equations (1) and (2):
Pf
(
Vf
)=
Qi
(
Vi
)  (1)
Vg=Vf+Vi
  (2)
combining these Equations (1) and (2) together, the following Equation (3)
Pf
(
Vf
)=
Qi
(
Vg−Vf
)  (3)
is derived.
FIG. 11A
illustrates a Pf−Vf characteristic (which is a so-called “hysteresis loop”) of the ferroelectric capacitor. In
FIG. 11A
, Pf values corresponding to increasing voltages are represented by the lower curve
1
, while Pf values corresponding to decreasing voltages are represented by the upper curve
2
. A voltage, at which Pf=0 C/cm
2
in the Pf−Vf characteristic, is called a “coercive voltage Vc”.
FIG. 11B
illustrates a Qi−Vi characteristic of the FET as a curve
51
. This characteristic can be easily obtained by a well-known computation method for an MOS capacitor.
By performing a symmetry transformation on this Qi−Vi characteristic about the Qi axis and shifting the resultant curve by Vg along the Vi axis, a Qi−(Vg−Vf) characteristic can be obtained. Thereafter, the Pf−Vf and Qi−(Vg−Vf) characteristics are plotted on the same graphic plane to obtain their intersection. As can be seen from Equation (3), this intersection represents the operating point of the FeFET. Supposing the voltage at the intersection is identified by Vx, Vf=Vx and Vi=Vg−Vx.
The operation of the FeFET will now be simulated by an operating point analysis technique using this graph.
First, it will be analyzed where the operating point is located when data “1” is written, i.e., a positive voltage Vg (>0 V) is applied to the control electrode.
FIG. 12A
illustrates a Pf−Vf characteristic
1
and
2
and a Qi−(Vg−Vf) characteristic
52
where a voltage Vg of 15 V is applied to the control electrode. As shown in
FIG. 12A
, the voltage Vx at the intersection
53
is 3 V, and vf=3 V. Accordingly, Vi=12 V is obtained by Equation (2).
Next, it will be analyzed where the operating point is located when data “0” is written, i.e., a negative voltage vg (<0 V) is applied to the control electrode.
FIG. 12B
illustrates a Pf−Vf characteristic
1
and
2
and a Qi−(Vg−Vf) characteristic
54
where a voltage vg of −15 V is applied to the control electrode. As shown in
FIG. 12B
, the voltage Vx at the intersection
55
is −3.5 V, and Vf =−3.5 V. Accordingly, Vi=−11.5 V is obtained by Equation (2).
If data is saved in such a state, the control electrode is floating. However, there is a voltage drop due to a leakage current flowing through the ferroelectric and FET and there is also a coupling capacitance between the electrodes. For that reason, the control electrode voltage Vg is believed to be almost 0 V. Thus, the following discussion will be based on the supposition that Vg=0 V (Vi=Vg−Vx≈−Vx) while the control electrode is floating.
FIG. 13
illustrates a Pf−Vf characteristic
1
and
2
and a Qi−(Vg−Vf) characteristic
56
, which represent the operation state of the

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