Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-26
2002-07-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S693000, C438S697000
Reexamination Certificate
active
06417102
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods of filling contact and other openings with electrically conductive material, and to semiconductor processing planarizing and other techniques.
BACKGROUND OF THE INVENTION
The invention primarily grew out of needs for making highly reliable, high density dynamic random access memory (DRAM) and other electrical contacts. Advanced semiconductor fabrication is employing increasing vertical circuit integration as designers continue to strive for circuit density maximization. Such typically includes multi-level metallization and interconnect schemes.
Electrical interconnect techniques typically require making electrical connection between metal or other conductive layers, or regions, which are present at different elevations within the substrate. Such interconnecting is typically conducted, in part, by etching a contact opening through insulating material to the lower elevation of a layer or conductive region. The significant increase in density of memory cells and vertical integration places very stringent requirements for contact fabrication technology. The increase in circuit density has resulted in narrower and deeper electrical contact openings between layers within the substrate, something commonly referred to as increasing aspect ratios. Such currently range from 1.5 to 5 and are expected to increase. Adequate contact coverage of electrically conductive materials ultimately placed within these deep and narrow contacts continues to challenge the designer in assuring adequate electrical connection between different elevation areas within the substrate.
As contact openings become narrower and deeper, it becomes more difficult for the artisan to completely fill the contact openings. An example of the problem is best understood with reference to the accompanying
FIGS. 1 and 2
. There illustrated is a semiconductor wafer fragment
10
comprised of a bulk substrate
12
and an overlying silicon dioxide layer
14
, such as borophosphosilicate glass (BPSG). Bulk substrate
12
includes a dopant diffusion region
16
to which electrical connection is to be made. A contact opening
18
is provided through BPSG layer
14
to active area
16
.
A thin layer
20
of titanium is deposited atop the wafer to within contact opening
18
. Titanium layer
20
is provided to function as a silicide formation layer at the base of contact
18
for reducing resistance. An undesired oxide layer (not shown) also typically forms atop diffusion region
16
. The deposited elemental titanium also functions to break-up this undesired oxide and thereafter form a titanium silicide with the silicon of substrate
12
to reduce contact resistance between active area
16
and subsequently deposited plug filling tungsten. Additionally, titanium layer
20
functions as an adhesion
ucleation layer for the subsequently deposited conductive material, for example tungsten. Tungsten does not readily deposit over silicon dioxide and exposed silicon substrate, and the intervening titanium layer
20
facilitates deposition and adhesion of tungsten thereto.
Titanium layer
20
is typically deposited by sputter deposition, and undesirably results in formation of contact projecting cusps
22
. This results in a back or re-entrant angle
24
being formed relative to contact opening
18
. A layer
26
of tungsten is subsequently deposited with the intent being to completely fill the remaining volume of contact opening
18
. Unfortunately, an undesired keyhole
28
typically forms, leaving a void within contact
18
.
Referring to
FIG. 2
, layers
26
and
20
are subsequently etched back by dry etch or chemical-mechanical polishing to form a contact-filling plug
30
. Undesirably, this typically opens-up the upper end of keyhole
28
. This undesirably creates a thin void which is difficult to clean and rinse during processing. Also in the final construction, the outer surface area of plug
30
is reduced due to the void created by keyhole
28
. This counters the desired goal of maximizing electrical contact with plug
30
with a subsequent layer for ultimately making electrical connection with active area
16
. Further, the etch back typically conducted to produce plug
30
undesirably over-etches titanium layer
20
, forming edge “fangs”
32
. Even where a desired overlying metal line and plug filling material constitute the same material deposited in a common step, undesired voids typically form within the contacts.
Prior art techniques have been developed which desirably cause some degree of reflow of the contact filling materials and/or overlying metal conductive lines to facilitate filling of contacts and eliminating voids. One such prior art method subjects the substrate to an extremely high pressure gas phase treatment within a sealed vessel. An example gas phase pressure is around 700 atmospheres and an example temperature of around 400° C. Such conditions apparently cause extrusion of the metal such that it reflows to a slight degree to 11 completely fill contacts, yet without melting to a point of completely losing its previously patterned shape outside of the contacts. One industry process of doing so is referred to as a “force fill” process.
However, such extreme gas pressures and treatment vessels create considerable safety problems to all those working in the vicinity of such vessels. Specifically, if a gas leak or crack were to develop in the reactor vessel, the rapidly expanding gas flowing through such crack could cause the reactor to completely blow apart much like a bomb, or alternately turn the reactor into a lethal projectile.
It would be desirable to overcome these and other problems associated with formation of electrically conductive contact plugs. Although the invention principally arose out of concerns specific to contact filling, the artisan will appreciate that the invention has other applicability in semiconductor processing with the invention only be limited by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.
SUMMARY OF INVENTION
In accordance with one aspect of the invention, a semiconductor processing method of treating a semiconductor wafer provides a wafer within a volume of liquid. The wafer has some electrically conductive material formed thereover. The volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere and at a temperature of at least 200° C. and below and within 10% of the melting point of the electrically conductive material. In accordance with another aspect, the volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere. After establishing the pressure of greater than 1 atmosphere, the pressure of the volume of liquid is lowered to a point effective to vaporize said liquid and the vapor is withdrawn from the chamber. In accordance with still another aspect, a semiconductor processing method of increasing planarity of an outer surface on a substrate comprises exposing the outer surface to a volume of liquid at a pressure of greater than about 200 atmospheres.
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patent: 3650823 (1972-03-01), Mead et al.
patent: 4581108 (1986-04-01), Kapur et al.
patent: 5434107 (1995-07-01), Paranjpe
patent: 5489372 (1996-02-01), Hirano
patent: 5994172 (1999-11-01), Ohtani et al.
patent: 6006763 (1999-12-01), Mori et al.
patent: 6191040 (1999-12-01), Glass
patent: 6046060 (2000-04-01), Budnaitis
Dixit, G.A., et al., “A Novel High Pressure Low Temperature Aluminum Plug Technology For Sub-0.5 &mgr;m Contact/Via Geometries”,I.E.E.E., p. 105; p. 208 (1994).
Butler, David, “Options for Multilevel Metallization”,Solid State Technology, pp. S7-S10 (Mar. 1996), including attached Product Brochure and Product Information on “Forcefill System” by Electrotech Ltd., Bristol, UK.
Dixit, Girish, A., “Application of High Pressure Extruded Aluminum to ULSI Metallization”,Semiconductor International, pp. 79-80, 82, 83-84 (Aug. 1995).
Burggraaf, Pieter, “Straightenin
Cathey David A.
Durcan Mark
Berry Renee R.
Nelms David
Wells St. John P.S.
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