Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2001-03-30
2002-06-04
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S096000, C327S525000
Reexamination Certificate
active
06400632
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a fuse element that allows information to be stored in a non-volatile manner.
2. Description of the Background Art
For example, a semiconductor memory device having memory cells arranged in an array form in row and column directions include a plurality of extra memory cell rows and memory cell columns. A system for improving the yield of chips on a wafer has been conventionally adopted in which deficient memory cells, memory cell rows, or memory cell columns caused by defects are replaced with the extra memory cell rows or memory cell columns for relief.
This system requires an internal circuit in which poor addresses sensed by a wafer test are stored in advance in a non-volatile manner in the chip, and the row and column addresses input at the time of use are monitored at all times and, when an input of poor addresses is sensed, they are replaced with the extra lines.
As the aforesaid internal circuit, an address sensing circuit is widely used which cuts a polysilicon wiring, an aluminum wiring, or the like with a laser beam, as disclosed, for example, in the document “IEEE Journal of Solid-State Circuits Vol. SC-18No. 5, October 1983, pp. 441-446”.
FIG. 32
is a circuit diagram illustrating a construction of a conventional address sensing circuit
500
.
Referring to
FIG. 32
, an address sensing circuit
500
includes fuse elements
502
.
0
to
502
.n each one end of which is connected to a node N
500
, and N-channel MOS transistors
504
.
0
to
504
.n whose drains are connected respectively to the other ends of the fuse elements
502
.
0
to
502
.n, whose gates receive addresses ADD<
0
> to ADD<n>, and whose sources are all connected to the ground voltage.
The address sensing circuit
500
further includes P-channel MOS transistors
506
,
508
connected in parallel between a node to which the power source voltage Vcc is given and the node N
500
, and an inverter
510
whose input is connected to the node N
500
and which outputs a sensing signal MIS.
A precharging signal PG is given to the gate of the P-channel MOS transistor
506
. The gate of the P-channel MOS transistor
508
receives the sensing signal MIS.
An address of positive logic and a complementary address, which is an inverted address thereof, are input via a fuse to a decoder of an extra column of the semiconductor memory device (hereafter referred to as an extra decoder). By cutting off the fuse corresponding to the address of a poor memory cell with a laser beam, the address of the poor memory cell is stored in a non-volatile manner.
On the other hand, the address sensing circuit
500
functions in such a manner that, when the input address coincides with the address corresponding to the poor memory cell stored in a non-volatile manner, a sensing signal MIS for inactivating the normal decoder connected to the poor column is output to replace the poor column with an extra column.
Here, an example has been given for a case in which a column is replaced; however, a similar construction is adopted in the case of replacing a poor row with an extra row.
Further, a fuse element is used also for tuning analog circuits and others whose characteristics change chip by chip. In this case also, the yield can be improved by tuning chip by chip.
The conventional fuse element requires an expensive laser cutter for cutting, and has a problem of poor precision in cutting the fuses. In order to solve these problems, an antifuse element is used in recent years. For example, U.S. Pat. No. 5,631,862 and 2000 IEEE International Solid-State Circuits Conference “WP 24.8 Antifuse EPROM Circuit for Field Programmable DRAM” disclose a circuit example that uses an antifuse element. The circuit disclosed in the latter document will be described hereafter.
FIG. 33
is a circuit diagram illustrating a construction of an antifuse program circuit
520
.
Referring to
FIG. 33
, an antifuse
526
receives a voltage Vpgm at one end thereof and the other end thereof is connected to a node N
502
. The antifuse
526
in its original state is in a non-conducted state between the two electrodes thereof. When a dielectric substance between the two electrodes is destroyed by allowing the voltage Vpgm to be a high voltage, an electrically conductive type path having a resistance value of about several K &OHgr; is formed between the two electrodes of the antifuse
526
.
In a normal operation mode, the voltage Vpgm is maintained at the power source voltage Vcc; however, in changing the antifuse
526
into a conducted state between the two electrodes (hereafter referred to as blowing), a high voltage is applied as the voltage Vpgm.
The signal SA is a signal for selecting whether the antifuse
526
is to be blown or not. In carrying out a reading operation, when the signal SNL is activated after the precharging signal PG is once activated to a L(low)-level to set the voltage of the node N
501
to the power source voltage Vcc, it is possible to read whether the antifuse
526
has been blown or not. The read data are latched by the latch circuit constructed with the inverters
544
,
546
.
FIG. 34
is an operation waveform diagram for describing a fuse blowing operation of the antifuse program circuit
520
shown in FIG.
33
.
Referring to
FIG. 34
, the signal PG is activated to the L-level at the time t
1
to initialize the voltage of the node N
501
.
Subsequently, the signal SA is set at a H(high)-level at the time t
2
to fix the voltage of the node N
501
at the L-level. Thereafter, the voltage Vpgm is set at a voltage VBP such that the antifuse
526
undergoes dielectric breakdown. Then, the antifuse
526
is blown.
FIG. 35
is an operation waveform diagram for describing an operation in the case where the fuse-blowing is not carried out.
Referring to
FIG. 35
, the signal PG is activated to the L-level at the time t
1
to t
2
to initialize the voltage of the node N
501
.
Next, the signal SA is maintained at the L-level without change at the time t
2
. This point is different from the case of
FIG. 34
in which the signal SA is activated to the H-level to carry out the fuse-blowing.
At the time t
2
, a high voltage is applied as the voltage Vpgm. However, the node N
501
is in a so-called floating state, and its level is at the H-level. Since the power source voltage Vcc is given to the gate of the N-channel MOS transistor
528
, the voltage difference Vgs between the gate and the source of the N-channel MOS transistor
528
is 0V, so that the N-channel MOS transistor
528
is in a non-conducted state. Therefore, the node N
502
is in a floating state, so that even if a high voltage is applied as the voltage Vpgm, the voltage of the node N
502
rises by capacitive coupling to become approximately the same voltage as the voltage Vpgm. For this reason, the voltage applied between the two electrodes of the antifuse
526
is a voltage V
5
of
FIG. 35
which is approximately near 0V, so that the antifuse
526
is not blown.
As described above, by performing the operations shown in
FIGS. 34 and 35
for the antifuse corresponding to each address, the address can be programmed.
Next, the reading operation will be described.
FIG. 36
is an operation waveform diagram for describing a reading operation of the antifuse program circuit
520
.
Referring to
FIGS. 33 and 36
, the voltage Vpgm is set at the power source voltage Vcc as an initial state, and the signal SA is set at the L-level.
Subsequently, at the time t
1
, the node N
501
is initialized by the signal PG.
At the time t
2
, the signal PG is inactivated to the H-level, and the node N
501
is brought to the H-level which is a floating state.
Subsequently, at the time t
3
, the signal SNL is set at the H-level. Then, if the antifuse
526
has not been blown, the voltage of the node N
501
is brought to the L-level by electric conduction of the N-channel MOS transistor
530
.
Thereafter, at the time t
4
, when the signal
Hidaka Hideto
Kato Hiroshi
Ooishi Tsukasa
Tanizaki Hiroaki
Tomishima Shigeki
Mai Son
McDermot, Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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