Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-08
2002-08-13
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000
Reexamination Certificate
active
06433391
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the manufacture of semiconductor structures and, more specifically, relates to the manufacture of semiconductor-on-insulator (SOI) structures.
BACKGROUND ART
Semiconductor-on-insulator (SOI) structures have several advantages over conventional bulk substrates: the elimination of latch-up, reduced short-channel effects, improved radiation hardness, dynamic coupling, lower parasitic junction capacitance, and simplified device isolation and fabrication. Such advantages allow semiconductor device manufacturers to produce low-voltage, low-power, high-speed devices thereon. For example, metal-oxide semiconductor field effect transistors (MOSFETs) are commonly formed on SOI structures. However, MOSFETs formed on such SOI structures suffer from a floating body effect (FBE).
Unlike bulk silicon MOSFETs, an SOI MOSFET is usually electrically floating in relation to the substrate. In a non-fully depleted MOSFET, carriers (holes in nMOSFETs and electrons in pMOSFETs) generated by impact ionization accumulate near the source/body junctions of the MOSFET. Eventually, sufficient carriers will accumulate to forward bias the body with respect to the source thus lowering the threshold voltage through the body-bias effect. Extra current will start flowing resulting in a “kink” in the I-V characteristics. The extra current flow reduces the achievable gain and dynamic swing in analog circuits, and gives rise to an abnormality in the transfer characteristics in digital circuits. Additionally, the FBE causes higher device leakages and undesirable transient effects.
One attempted solution to solve problems due to the FBE is to provide a contact to the body for hole current collection. However, currently available hole collection schemes, including the use of a side-contact or a mosaic source are very inefficient and consume significant amounts of wafer area.
Therefore, there exists a strong need in the art for an SOI structure with a buried insulator layer that bleeds off extra carriers from a channel to the main substrate.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a semiconductor-on-insulator (SOI) structure having a buried insulator layer disposed between a semiconductor substrate and a semiconductor layer and an interface between the oxide layer and the semiconductor layer that bleeds off extra carriers.
According to another aspect of the invention, the invention is a method of fabricating a semiconductor-on-insulator (SOI) structure having an insulator layer disposed between a semiconductor substrate and a semiconductor layer. The method includes the steps of depositing an insulator layer on a first semiconductor substrate. Further, the method includes the step of creating a zone of weakness under a surface of a second semiconductor substrate. Next, the method requires the placing of the second semiconductor substrate on top of the first semiconductor substrate such that the oxide layer of the first semiconductor substrate is in contact with a surface of the second semiconductor substrate. The method also includes the step of breaking the zone of weakness of the second semiconductor substrate and repairing a damaged surface resulting from the breaking of the zone of weakness of the second semiconductor substrate.
According to another aspect of the invention, the invention is a method of fabricating an SOI structure as described above. However, the method step of repairing the surface resulting from the breaking of the zone of weakness further includes the step of polishing the surface in order to remove residual weak zone damage.
According to another aspect of the invention, the invention is a method of fabricating an SOI structure as described in the first method above. The method further includes the additional step of fusing the insulator layer of the first semiconductor substrate with the second semiconductor substrate.
REFERENCES:
patent: 6004837 (1999-12-01), Gambino et al.
patent: 6210998 (2001-04-01), Son
patent: 6225667 (2001-05-01), Buynoski et al.
Jean-Pierre Colinge, Silicon-On-Insulator Technology: Materials to VLSI, 2ndEdition, 1997; Chapter 3: SOI Materials Characterization pp. 95-96 and Chapter 7: The SOI MOSFET Operating in a Harsh Environment p. 228.
En William George
Ju Dong-Hyuk
Advanced Micro Devices , Inc.
Renner , Otto, Boisselle & Sklar, LLP
Tsai Jey
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