Semiconductor device and a process for designing a mask

Details Semiconductor device and a process for designing a mask Semiconductor device and a process for designing a mask

1999-06-29

2002-05-28

Wong, Don (Department: 2821)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S621000, C257S752000, C257S758000

Reexamination Certificate

active

06396158

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to semiconductor devices and masks, and more particularly, to semiconductor devices and masks having dummy features.
RELATED ART
Polishing is used to planarize surfaces in forming semiconductor devices. Traditionally, no tiling has been used in forming semiconductor devices. When no tiling is used, polishing causes dishing or other problems related to nonuniform thickness across a semiconductor device substrate. These problems include exceeding the depth of focus for lithography or etchrelated concerns that are illustrated in FIG.
1
.
FIG. 1
includes a substrate that includes a conductive layer
11
. An insulating layer
12
is formed and patterned with openings extending to the conductive layer
11
. A conductive fill material (e.g., tungsten or the like) is deposited into the openings and polished to form conductive plugs
13
. The polishing can erode more of the insulating layer
12
where the conductive plugs are closely spaced. An insulating layer
16
is then formed over the conductive plugs
13
. The upper surface of the insulating layer
16
is planar.
Openings
17
are then formed. In some locations, openings do not extend completely to all the conductive plugs
13
because of the erosion, thereby leaving an insulating gap
19
between an opening
17
and its underlying conductive plug
13
as shown in FIG.
1
. An electrical open would be formed. If the etch is continued to remove gap
19
, the conductive plugs
13
that are exposed earlier are overetched, typically resulting in high contact resistance. Therefore, the nonuniformity in thickness, caused in part by polishing, can result in electrical opens, high resistance contacts, electrical shorts, or other leakage paths.
Dummy features have been used as an attempt to solve the problems related to dishing and other accumulated thickness effects. Dummy features used to aid polishing are formed by “tiling” because, from a top view of the semiconductor device, the pattern of dummy features looks like tiles. The process for tiling typically includes creating a circuit layout, defining a buffer zone (typically in a range of approximately 5-10 microns) around active features within the layout, and combining the circuit layout with the minimum zone to determine excluded areas. All other areas are available for tiling.
Regardless of circuit density, tiling is used if the distance between any of active features is at or above a minimum width. Typically, the minimum width is no more than ten microns, and can be approximately ten microns. Tiles or at least partial tiles are placed in available areas at least five microns wide. The tiling pattern (i.e., size and density of tiles) is usually the same across a semiconductor device. See FIG. 5 in each of U.S. Pat. No. 5,278,105 and European Published Patent Application Number 0 712 156 (1996). Although portions of tiles are missing, the same feature density is used.


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Andrew B. Kahng et al., “Filling and Slotting: Analysis and Algorithms”, ISPD 98 Monterey CA USA, pp. 95-102.
Brian E. Stine et al., “The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes”, 1998 IEEE, pp. 665-679.
B. Stine et al., “A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes”, Proc. CMP-MIC, Santa Clara, CA, Feb. 1997.
Andrew B. Kahng et al., “Filling Algorithms and Analyses for Layout Density Control”, 1999 IEEE, vol. 18, No. 4, Apr., 1999, pp. 445-462.
Stine et al, “The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes”, IEEE Transactions on Electron Devices, vol. 45, No. 3, pp. 665-679 (1998).
Wei Huang, et al., “A Layout Advisor for Timing-Critical Bus Routing1”, 1997 IEEE, pp. 210-214.
George Y. Liu et al., “Chip-Level CMP Modeling And Smart Dummy For HDP And Conformal CVD Films”, Proceedings of CMP-MIC Feb. 11, 1999, (8 pages).
PCT International Search Report: PCT/US00/14293 (6 pp.).

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