Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-29
2002-03-19
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S147000
Reexamination Certificate
active
06359306
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-186546, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing thereof.
FIGS. 12A-12C
are drawings used for describing a process for manufacturing a conventional trench-MOS (Metal Oxide Semiconductor) gate structure.
FIGS. 12A and 12B
are cross-sectional views of a device of the trench-MOS gate structure in its manufacturing process, and
FIG. 12C
is a perspective view of the device.
In the conventional method of manufacturing, as shown in
FIG. 12A
, a p-type base layer
2
is formed by diffusion in a surface portion of an n-type high-resistance substrate
1
, and then an n-type source layer
3
is selectively formed by diffusion in a surface portion of the p-type base layer
2
. Thereafter, a trench for a MOS gate, which penetrates the n-type source layer
3
and the p-type base layer
2
and communicates with the n-type high-resistance substrate
1
, is formed, and the entire surface of the substrate
1
including the trench is covered with a gate insulating film
4
(FIG.
12
A). Thereafter, a gate electrode
5
is buried in the trench, and then an insulating film
6
is deposited to cover the gate electrode
5
(FIG.
12
A). Thereafter, as shown in
FIG. 12B
, a contact window is formed and then, as shown in
FIG. 12C
, a MOS gate structure is formed by forming an emitter electrode
10
on the surface of the substrate
1
. In the process of manufacturing the trench-MOS gate structure, a margin for mask alignment was required as shown in
FIG. 12A
, so that the emitter electrode
10
and the p-type base layer
2
are connected. Further, as shown in
FIG. 12B
, it was necessary to provide a margin for mask alignment in order to prevent short circuit between the gate electrode
5
and the emitter electrode
10
. Since there were these alignment margins, scale down of the device was difficult, and property improvement such as reduction of the on-state resistance was difficult.
As described above, in a process of manufacturing a semiconductor device having a conventional trench gate structure, it was necessary to provide margins for aligning masks for formation of trench, n-type source layer and contact window. Therefore, there was the problem that scale down of the device structure was restricted by the margins for mask alignment.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in consideration of such circumstances, and has its object to provide a semiconductor device and a method of manufacturing thereof, which enables scale down of a device structure.
Therefore, in order to solve the above problem, the present invention is characterized in that mask alignment is unnecessary, scale down is possible and device property is improved by alternately forming trenches and source layers for contact in a region between parallel trench gates.
Specifically, according to a first aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity-type base layer;
a second conductivity-type base layer formed on the first conductivity-type base layer;
a first conductivity-type source layer formed on the second conductivity-type base layer;
a plurality of first trenches formed in parallel to each other, which penetrate from a surface of the first conductivity-type source layer through the first conductivity-type source layer and the second conductivity-type base layer and reach the first conductivity-type base layer;
gate insulating films formed on wall surfaces of the first trenches;
gate electrodes formed within the first trenches and on the second conductivity-type base layer via the gate insulating films;
a plurality of second trenches which penetrate from the surface of the first conductivity-type source layer through the first conductivity-type source layer and reach the second conductivity-type base layer; and
a first main electrode formed within the second trenches and electrically connected to the first conductivity-type source layer and the second conductivity-type base layer,
wherein portions of the second trenches and portions of the first conductivity-type source layer are alternately arranged in regions among the first trenches.
In the semiconductor device according to the first aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches, the second conductivity-type contact layers having an impurity concentration higher than the second conductivity-type base layer.
In the semiconductor device according to the first aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches and second conductivity-type block layers formed in surface portions of the first conductivity-type source layer, the second conductivity-type contact layers and the second conductivity-type block layers having an impurity concentration higher than the second conductivity-type base layer.
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity-type base layer;
a second conductivity-type base layer formed on the first conductivity-type base layer;
a first conductivity-type source layer formed on the second conductivity-type base layer;
a plurality of first trenches formed in parallel to each other, which penetrate from a surface of the first conductivity-type source layer through the first conductivity-type source layer and the second conductivity-type base layer and reach the first conductivity-type base layer;
gate insulating films formed on wall surfaces of the first trenches;
gate electrodes formed within the first trenches and on the second conductivity-type base layer via the gate insulating films;
a plurality of second trenches which penetrate from the surface of the first conductivity-type source layer through the first conductivity-type source layer and reach the second conductivity-type base layer;
a first main electrode formed within the second trenches and electrically connected to the first conductivity-type source layer and the second conductivity-type base layer;
a high impurity concentration base layer and a second conductivity-type collector layer superposed on a surface of the first conductivity-type base layer, which surface is opposed to a surface thereof on which the second conductivity-type base layer is formed, the high impurity concentration base layer having an impurity concentration higher than the first conductivity-type base layer and being of the first conductivity-type; and
a second main electrode formed on the second conductivity-type collector layer,
wherein portions of the second trenches and portions of the first conductivity-type source layer are alternately arranged in regions among the first trenches.
In the semiconductor device according to the second aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches, the second conductivity-type contact layers having an impurity concentration higher than the second conductivity-type base layer.
In the semiconductor device according to the second aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches and second conductivity-type block layers formed in surface portions of the first conductivity-type source layer, the second conductivity-type contact layers and the second
Kabushiki Kaisha Toshiba
Loke Steven
Nguyen Cuong Q
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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