Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-08-26
2002-03-19
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S773000
Reexamination Certificate
active
06360346
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a storage unit such as a data-erasable (reloadable) non-volatile semiconductor memory, and a method of checking or examining the storage unit.
2. Description of the Related Art
In recent years, semiconductor memories such as a flash memory have come into widespread use for storage units where data is electrically erasable and rewritable.
The flash memory is a semiconductor memory composed of a cell array made by arranging a large number of (usually, approximately 65,000,000 cells) storage elements (memory cells) each comprising charge storage layers formed in a laminated condition on a semiconductor substrate and control gates for storing information. The information (data) is stored in relation to the quantity of charge to be accumulated in the aforesaid charge storage layers.
A significant object about such a semiconductor memory is to prevent the decrease in its reliability with the increase in integration and densification, particularly, for example, the occurrence of cell defectives due to the increase in the number of write/read operations and with the passage of time.
For this reason, an error correcting circuit using an error correcting code such as a hamming code has been incorporated into the interior of a semiconductor memory.
Such error correction is a way in which redundant data, called checking data, is added to information data to be stored which in turn, is encoded so that errors existing in the encoded data (code data) are corrected through the use of the checking data.
FIG. 1
is a block diagram showing an arrangement of a prior flash memory into which incorporated an error corrector using the aforesaid compacted hamming code.
This flash memory, designated at numeral
70
, is made up of an encoder
61
for hamming-encoding data s
21
inputted to correct one error within a code, a cell array
63
serving as a storage section to store write data s
22
manning-encoded in the encoder
61
, and a hamming decoder
65
for decoding readout data s
23
read out from the cell array
63
and hamming-encoded.
Writing data in this flash memory
70
takes place as follows. That is, the inputted data s
21
is first put in the encoder
61
which in turn, adds 10-bits checking data at every inputted data comprising 512 bits as shown in
FIG. 2
, which will be described herein later, to convert the data into a compacted hamming code, and subsequently, outputs it as the write data s
22
. This write data s
22
is written the cell array
63
.
On the other hand, reading out data from the flash memory
70
is done as follows. The readout data s
23
read out from the cell array
63
is inputted into the hamming code decoder
65
, and if the number of errors in one code is below 1, is outputted as output data s
24
after being subjected to error correction.
FIG. 2
shows one example of information data to which checking data is added.
For instance, in the case of using compacted hamming code, checking data
32
of 10 bits is added to information data
31
of 512 bits to make a code comprising 522 bits in total, so that one error occurring within that code becomes correctable.
Through the use of this error correction, even if the cell defective occurs to some extent due to a change with the passage of time of a storage unit such as a semiconductor memory, it is possible to prevent the presence of readout error in written data.
However, for the correction of many errors, the error correcting code is required to have much checking error being generally redundant data, and hence, many cells are needed to use and simultaneously, the error corrector becomes larger in circuit scale.
FIG. 3
exemplifies an arrangement of a cell array of the aforesaid flash memory.
In this example, the storage area of the cell array
63
is divided into blocks
65
,
66
,
67
, . . . ,
69
, each of which is composed of areas called cells. For instance, in the block
65
, numerals
65
a
,
65
b
, . . . represent the cells, respectively.
As mentioned above, in general, the whole cell array is divided into some blocks, and usually, is made up of 1000 blocks each including approximately 65000 cells.
In this cell array, the block including a defective cell is detected as a defective block. Further, in the examination of the cell array to be done before being put on the market, if the rate of the defective blocks to the total number of blocks of the cell array is below a predetermined value (usually, approximately 1%), that cell array is put on the market as an acceptance.
FIG. 4
is an illustration of one example of processing procedures of a prior checking method for detecting defective cells of a semiconductor memory such as flash memory to count the number of defective cells.
The processing starts at a step ST
21
to set the number of defective blocks at zero.
Subsequently, a step ST
22
follows to read out data previously written as checking data by the quantity corresponding to one block.
Furthermore, a step ST
23
follows to decide whether or not there is an error within the data corresponding to one block read out in the step ST
22
. If there is the error, the processing advances to a step ST
24
to increment the count value forming the number of defective blocks by one, then followed by a step ST
25
. On the other hand, if the decision shows no error, the operational flow directly proceeds to a step ST
25
.
The step ST
25
is for deciding or not the all the blocks undergo the error detection. If no completion of the error detection for all the blocks, the operational flow returns to a step ST
22
to repeat the processing up to the step ST
25
. On the other hand, if the error detection covers all the blocks, the operational flow goes to a step ST
26
.
In the step ST
26
, decision is made, for example, on whether the rate of the number of defective blocks to the total number of blocks of the semiconductor memory is below 1%. If satisfying this requirement, an acceptance decision is made in a step ST
27
, whereas, of not satisfying the requirement, a defect decision is made in a step ST
28
. The examination terminates at this time.
However, since the above-mentioned prior hamming code employed as an error correcting code for a semiconductor memory such as a flash memory can correct only one error in the data corresponding to one code, there is a problem in that its error correction ability is insufficient for attaining a high reliability.
In addition, as mentioned before, as the inferiority (defective condition) of the semiconductor memory, in addition to the passage-of-time inferiority such as the cell inferiority attributed to the increase in the write/erase frequency, there is the cell inferiority occurring in the manufacturing processes.
For this reason, since the prior semiconductor memory using the aforesaid error corrector can reduce the cell inferiority resulting from a change with the passage of time but can not reduce the inferiority occurring in manufacturing, difficulty is experienced to prevent the deterioration of the productivity due to the impairment of the yield.
Moreover, because of the use of the error correcting code such as the hamming code which can correct one error within a code, in the case of correcting the readout error caused by the cell inferiority at the manufacturing, the surplus power for correcting the readout error resulting from the change with the passage of time may disappear.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been developed in order to eliminate such problems, and it is an object of this invention to provide a storage unit with a high reliability which is capable of preventing the occurrence of readout error in written data even if two or more errors occur within a code due to the change with the passage of time or the like.
Another object of this invention is to provide a storage unit with a high reliability which has an error correction ability to correct the errors resulting from the inferiority in manufacturing and the errors caused by the inferiority
Hattori Masayuki
Miyauchi Toshiyuki
Baker Stephen M.
Frommer William S.
Frommer & Lawrence & Haug LLP
Simon Darren M.
Sony Corporation
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