EEPROM cell with self-aligned tunneling window

Details EEPROM cell with self-aligned tunneling window EEPROM cell with self-aligned tunneling window

1998-10-09

2002-07-23

Hardy, David (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S321000

Reexamination Certificate

active

06424003

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electrically, erasable programmable read-only memory (EEPROM) cells for use in complex programmable logic device (CPLD) technology. More particularly, it relates to an improved EEPROM cell having a self-aligned tunneling window which permits smaller layout size, lower programming and erasing voltages, and reduced manufacturing costs.
2. Description of the Prior Art
As is generally known, EEPROM cells have been widely used in recent years in complex programmable logic devices (CPLDs). Most conventional EEPROM cells include three transistors consisting of a Program or Write transistor, a Read transistor, and a Sense transistor. The programming and erasing of the sense transistor is performed through a tunneling window by using a high voltage. In order to prevent breakdown of the sense transistor being operated in such a high voltage environment, the gate oxide thereof is required to be relatively thick on the order of 150-200 Å. In addition, since the gates of both the Program transistor and Read transistor are generally connected together and further joined to a wordline, which also has applied thereto a high voltage, the gate oxide thickness of the Read transistor must also be made relatively thick (i.e., 150-200 Å).
Further, in view of the trend of manufacturing integrated circuit memory devices with higher and higher densities, there exists a continuing need of scaling-down (reducing component size) of the transistors in order to have smaller and smaller memory cells. However, due to the fact that conventional EEPROMs require transistors having relatively thick oxide layers, effective scaling down of the conventional EEPROM devices cannot be achieved. Moreover, the EEPROM devices commonly require the formation of tunnel capacitors which include tunnel oxide layers on the substrate. Such tunnel oxide layers usually cannot be scaled down in thickness because significant endurance and data retention problems arise when the tunnel oxide layers are made too thin. As a result, there is also created a limitation on increasing the speed of the programming and erasing operations performed on the EEPROM based CPLDs.
Such a typical prior art EEPROM of the aforementioned type is described and illustrated in U.S. Pat. No. 4,924,278 to Stewart Logie and entitled “EEPROM Using Merged Source and Control Gate.” This '278 patent is assigned to the same assignee as in the present invention and is hereby incorporated by reference. In FIG. 2 of the '278 patent, there is shown a structure for an EEPROM memory cell 10 utilizing a single poly-Si floating gate 38. The poly-Si floating gate is capacitively coupled to a source of the sense transistor 30 via gate oxide layer 37 (approximately 300 Å in thickness) and is also capacitively coupled to source 34 of the write transistor 20 via tunnel oxide layer 55 (approximately 90 Å in thickness).
Therefore, it would be desirable to provide an improved EEPROM cell which permits a smaller layout size, can be programmed and erased using a lower voltage than the conventional EEPROM cell, and can be scaled down so as to reduce cell height and cell parasitic capacitance. Further, it would be expedient that the improved EEPROM cell be relatively easier and less costly to manufacture and assemble.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an improved EEPROM cell having a self-aligned tunneling window which overcomes the problems of the prior art.
It is an object of the present invention to provide an improved EEPROM cell having a self-aligned tunneling window which can be manufactured at relatively lower costs due to the use of a non-critical layer mask for the tunneling window.
It is another object of the present invention to provide an improved EEPROM cell which has a higher coupling ratio than the conventional EEPROM cell so as to allow scaling-down of the cell layout size.
It is still another object of the present invention to provide an improved EEPROM cell which is scalable so as to reduce cell height and cell parasitic capacitance.
It is yet still another object of the present invention to provide an improved EEPROM cell which has a higher injection efficiency than the conventional EEPROM cell so as to allow use of lower programming and erasing voltages.
In accordance with a preferred embodiment of the present invention, there is provided an EEPROM cell which includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The tunneling oxide layer defines a tunneling window which allows for programming and erasing of the floating gate by tunneling electrons therethrough. The programmable junction region has a width dimension and length dimension so as to define a first area. The tunneling window has a width dimension and a length dimension so as to define a second area. The floating gate has a width dimension and a length dimension so as to form a third area.
The width dimension of the tunneling window is made greater than the width dimension of the programmable junction region so as to overlap the programmable junction region. The length dimension of the tunneling window is made to be less than the length of the programmable junction region so as to be confined within the length dimension of the programmable junction region. The length dimension of the floating gate is made to be less than the length dimension of the tunneling window so that the tunneling window is overlapping the floating gate. The width dimension of the floating gate is made to be larger than the width dimension of the tunneling window so that the floating gate is overlapping the tunneling window. As a result, the tunneling window is self-aligned by edges forming the length dimension of the floating gate so as to form a self-aligned tunneling window.


REFERENCES:
patent: 4924278 (1990-05-01), Logie
patent: 5844269 (1998-12-01), Kuo
patent: 5917215 (1999-06-01), Chuang et al.
patent: 5953254 (1999-09-01), Pourkeramati
patent: 8-097302 (1996-04-01), None

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