Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-02
2002-03-12
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06357035
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to schemes for the automated design of programmable devices and/or components thereof. In particular, the schemes described herein may be applied to develop programmable interconnect matrices for complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs) and other similar devices.
BACKGROUND
Modem integrated circuit designers are often confronted with the problem of developing new circuit/component designs in as short a time as possible in order to minimize product time to market. Although complicated, often this task becomes one of fitting a desired set of circuit components into as small an area as possible and arranging interconnecting conductors between those elements in a manner that minimizes the lengths of the conductive paths. To compound this problem, the design solution is usually subject to a minimum spacing geometry, dictated by the resolution limits (and other technology factors) of the fabrication process employed. When a designer develops a new circuit or component, he/she typically begins by creating a schematic for the design. Such design processes have been automated to some degree for a number of years and a typical schematic produced through such processes usually consists of symbols representing the basic units of the design connected together with signals (or nets—short for networks). The symbols are usually chosen from a library of parts that the designer draws upon to build the schematic. The interconnection of the symbols and the signals (e.g., as stored in a design database) creates the connections needed to specify the design such that a netlist can be derived from the connections. The netlist can then be used to create a simulation model of the design to verify its operation before the actual component is built.
The manner in which the schematic representation of the overall circuit is developed may vary depending upon whether fully custom or semi-custom circuit elements need to be employed in the design. Thus, circuit designers often begin by searching a standard library of circuit elements to see if any will match the new circuit's requirements. The search may begin at a relatively high level to determine whether any previously defined circuit elements satisfy the needed chip-level or lower level (called “cells”) architectures. The number of hierarchical levels of cell structure will depend on the nature and complexity of the circuitry being designed.
If matching cells are found, the designer can proceed to synthesize the circuit. Otherwise, the designer may be required to build semi-custom cells from available low-level cells. In the event no existing circuit elements can satisfy the necessary design requirements, the designer may be forced to develop custom solutions. For example, decoding logic used in memory devices are typically custom implementations. Once the circuit elements have been chosen, the circuit is synthesized and optimized for a given set of technology rules (i.e., the design rules that describe limitations of the fabrication processes to be used). Commercial computer programs for performing such routines are available and are commonly used to perform such tasks.
The netlist produced during the synthesis and optimization process can be used to provide the information needed by a routing software package to complete the actual design. The routing software will create the physical connection data to create the layer information needed for the component specified by the design. The resulting design may then be simulated to test its behavior and, if necessary, the design can be modified to meet target design goals.
Once a design has been approved through simulation, tape out may be ordered. In the tape out process, the symbolic representation of the circuit is translated into an actual layout using a commercial layout editor program. As with the synthesis programs, layout editors utilize tables of design rules that are specific to the ultimate manufacturing process to be used to produce computer-readable files (masks) that can be used in the fabrication of the integrated circuit.
This conventional design methodology is flawed in as much as it requires that the designer be familiar with the specifics of the design language used to specify the components of the design. As design languages evolve and are replaced by new languages, this forces designers to relearn these languages. Further, this design procedure becomes tedious when designers are faced with developing an entire family of components, individual units of which may share some similarities but likely differ in other regards. Moreover, although conventional simulation tools often perform better (i.e., provide results more quickly) when the underlying circuit design is specified in terms of a hierarchical data structure, most conventional design tools do not provide such output. Rather, conventional design tools tend to provide so-called “flattened” data structures. Thus, simulation times (and, hence, overall design times) are often unnecessarily long.
Further deficiencies of these conventional design processes are also apparent where the circuit being designed is a CPLD, FPGS or similar device. CPLDs and other programmable logic devices rely on programmable interconnect matrices (PIMs) or similar interconnect paths to route signals within the device. In the past, see, e.g., U.S. Pat. No. 5,068,603, such PIMs have been organized as mask-defined, metalized interconnection arrays, which constitute multi-plane grids of metal-based routing lines and mask programmed interconnect segments. The mask programmed interconnect segments are included within or excluded from the programmable device in an automated fashion according to a computer-based design tool. The process by which interconnect segments are included or excluded is structured in such a manner that a chip manufacturer is able to provide an instruction tape to an automated mask-defining machine to produce the device.
Although useful, such schemes are manually intensive in as much as designers are forced to determine the layouts (and/or schematics) for the connections within the PIM before the automated tools can be used. Accordingly, what is needed is a scheme that allows for automation of such processes.
SUMMARY OF THE INVENTION
A programmable interconnect matrix (PIM) design, layout, schematic, netlist, abstract or other equivalent circuit representation (hereinafter “layout”) is hierarchically generated by selecting one or more PIM layout tiles from a plurality of different PIM layout tiles, and automatically compiling a plurality of the selected PIM layout tiles into a PIM layout. In some cases, the PIM layout tiles can be heterogeneous. Generally, the PIM layout includes a PIM array having one of a plurality of different sizes (e.g., n rows by m columns, n and m>1). In other embodiments, a PIM connection scheme is generated by automatically compiling a plurality of PIM layout tiles into a PIM layout, then programming interconnects of the PIM according to a mapping table specifying desired interconnections. This scheme may include generating the mapping table with software configured to optimize connections and/or routability and/or automatically generating a PIM layout database from the PIM connection scheme. Either or both of these methodologies may be embodied as a set of computer-readable instructions for performing the methods.
Other features and advantages of the present invention are described below with reference to the accompanying drawings.
REFERENCES:
patent: 5068603 (1991-11-01), Mahoney
patent: 5943488 (1999-08-01), Raza
Gowni Shiva P.
Patel Alpesh B.
Cypress Semiconductor Corp.
Le Thong
Nelms David
Wagner , Murabito & Hao LLP
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