Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
1999-06-08
2002-05-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S243000, C205S124000, C216S041000, C216S042000, C216S043000, C216S044000, C216S047000, C216S048000, C216S049000, C216S051000
Reexamination Certificate
active
06387771
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to etch hard masks formed by low temperature oxidation of metals.
2. Description of the Related Art
Trench formation in semiconductor fabrication is often limited by the capabilities of a mask used to form the trench or other component of a semiconductor wafer. To describe this in more detail, an illustrative example of deep trench etching is explained. Deep trenches are used to include a storage node for a deep trench capacitor. To increase the capacitance of a deep trench capacitor, it is advantageous to increase the surface area of the storage node. One way to do this is to increase a depth of the deep trench since the substrate which includes deep trenches can provide depth without impact to the layout area of the substrate. The deep trench (DT) etch depth is currently limited by mask erosion as explained below.
Referring to
FIG. 1
, a memory device
10
includes a substrate
12
having a pad stack
11
formed thereon. Substrate
12
is preferably a monocrystalline silicon substrate. Pad stack
11
includes an oxide layer
14
and a nitride layer
16
. A hard mask layer
18
is deposited on pad stack
11
. Hard mask
18
typically includes boron doped silicate glass (BSG). Hard mask
18
is patterned using lithographic techniques known to those skilled in the art to form holes
15
where deep trenches
17
will be formed. Formation of trench
17
is preferably formed by employing an anisotropic etch, such as a reactive ion etch (RIE).
Trench
17
is etched into substrate
12
. During this process, however, hard mask
18
is eroded away which may cause collateral damage to areas adjacent to the position of trench
17
. The longer etching occurs, the higher the risk of eroding away hard mask
18
.
To increase the amount of time for etching, a thicker hard mask
18
may be used. However, this increases process time and does not necessarily provide a deeper trench.
Therefore, a need exists for a more economical hard mask employed for etching which has increased selectivity such that etching time is increased without significant erosion of the hard mask.
SUMMARY OF THE INVENTION
A method for forming a valve metal oxide for semiconductor fabrication in accordance with the present invention includes the steps of providing a semiconductor wafer, depositing a valve metal material on the wafer, placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the valve metal material to form a metal oxide when a potential difference is provided between the valve metal material and the solution and processing the wafer using the metal oxide layer.
A method for etching trenches in a semiconductor substrate, in accordance with the present invention, includes the steps of providing a semiconductor substrate, forming a pad stack of the substrate, depositing a valve metal material on the pad stack, placing the substrate in an electrochemical cell such that a solution including electrolytes interacts with the valve metal material to form a metal oxide when a potential difference is provided between the valve metal material and the solution, and employing the metal oxide as an etch mask for etching trenches into the substrate.
Another method for forming a valve metal oxide for semiconductor fabrication, in accordance with the present invention, includes the steps of providing a semiconductor wafer including a substrate having at least one layer formed thereon, depositing a dielectric layer on the at least one layer, depositing a valve metal material on the dielectric layer, oxidizing the valve metal material by placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the valve metal material to form a metal oxide when a potential difference is provided between the valve metal material and the solution, the dielectric layer for providing protection for the at least one layer during the oxidizing step, and processing the wafer using the metal oxide layer.
In alternate methods, the step of depositing a valve metal material may include depositing a valve metal material selected from the group consisting of aluminum, niobium, tantalum, titanium, titanium nitride, hafnium and zirconium. The method may include the step of applying a voltage between the valve metal material and the solution to create the potential difference such that the voltage applied controls the thickness of the metal oxide. The solution may include an acetate buffer in aqueous solution. The acetate buffer solution preferably has a pH of between about 4 and about 7. The step of placing the wafer in an electrochemical cell may include the steps of placing the wafer in an electrochemical cell such that the wafer has an exposed surface area of valve metal, and providing a counter electrode in the solution having a greater exposed surface area than the exposed surface area of the valve metal.
The step of placing the wafer in an electrochemical cell may include the step of sealing other than exposed areas of the valve metal material to prevent contact with the solution. The solution which includes electrolytes preferably interacts with the valve metal material to form the metal oxide at about room temperature. The step of processing the wafer using the metal oxide layer may include the step of employing the metal oxide layer as an etch mask and/or etch stop. The step of employing the metal oxide as an etch mask for etching trenches into the substrate may include the step of patterning the valve metal material to open holes at locations for the trenches. The step of employing the metal oxide as an etch mask for etching trenches into the substrate may include the step of patterning the metal oxide to open holes at locations for the trenches. The step of processing the wafer may include the step of patterning the valve metal material to open holes at locations for trenches to employ the metal oxide as an etch mask. The step of processing the wafer may include the step of patterning the metal oxide to open holes at locations for trenches to employ the metal oxide as an etch mask.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
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Genz Oliver
Michaelis Alexander
Infineon - Technologies AG
Kennedy Jennifer M.
Niebling John F.
Paschburg Donald B.
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