Semiconductor memory and method of driving semiconductor memory

Details Semiconductor memory and method of driving semiconductor memory Semiconductor memory and method of driving semiconductor memory

2001-06-29

2002-05-28

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S310000, C257S314000, C257S315000

Reexamination Certificate

active

06396095

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a nonvolatile semiconductor memory device implemented as a field effect transistor including a ferroelectric film at its gate, and a method of driving the device.
BACKGROUND ART
A known field effect transistor with a ferroelectric film at its gate (which will be herein referred to as a “ferroelectric FET”) will be described with reference to FIG.
4
.
As shown in
FIG. 4
, the ferroelectric FET includes: insulating film
4
as a contact layer; ferroelectric film
3
; and gate electrode
15
that have been formed in this order on a silicon substrate
8
in which source/drain regions
5
and
6
have been defined. A channel region
7
is defined in part of the silicon substrate
8
between the source/drain regions
5
and
6
. In this structure, if up or down polarization is created in the ferroelectric film
3
and the threshold voltage of the ferroelectric FET can be set to one of two different values corresponding to these two polarization states, the up or down polarization existing in the ferroelectric film
3
is retained so long as the polarization state of the ferroelectric film
3
is retainable. Thus, data is stored in the ferroelectric FET.
As shown in
FIG. 5
, a memory cell is formed at each intersection of a matrix array by connecting word line W, bit line B, and source line S to the gate electrode
15
, drain region
6
and source region
5
of the ferroelectric FET, respectively.
FIG. 6
shows a planar layout for a memory cell array where the memory cells are arranged in matrix. In
FIG. 6
, M
11
, M
12
, M
21
and M
22
denote ferroelectric FETs as memory cells C
11
, C
12
, C
21
and C
22
, each of which is located at an intersection of the memory cell array. W
1
denotes a word line connected to the gates of the ferroelectric FETs M
11
and M
12
. W
2
denotes a word line connected to the gates of the ferroelectric FETs M
21
and M
22
. S
1
denotes a source line connected to the sources of the ferroelectric FETs M
11
and M
12
. S
2
denotes a source line connected to the sources of the ferroelectric FETs M
21
and M
22
. B
1
denotes a bit line connected to the drains of the ferroelectric FETs M
11
and M
21
. And B
2
denotes a bit line connected to the drains of the ferroelectric FETs M
12
and M
22
.
The logical state of a selected memory cell is determined depending on whether the ferroelectric FET of the memory cell is ON or OFF. The ON or OFF state of a ferroelectric FET is determined depending on whether or not the channel region
7
of the ferroelectric FET is electrically continuous. A gate voltage, turning the ferroelectric FET ON in one of the two polarization states exhibited by the ferroelectric film
3
upon the application of the gate voltage to the gate electrode
15
of the ferroelectric FET or OFF in the other polarization state, exists between the two mutually different threshold voltages. Thus, when such a gate voltage is applied to the gate electrode
15
, the logical state of the ferroelectric FET in ON state is supposed to be “1” and that of the FET in OFF state “0”, respectively.
To know the logical state retained on the memory cell C
11
shown in
FIG. 6
, for example, on this condition, the bit line B
1
is discharged to have a low potential, and then the voltage on the source line S
1
is raised to a read voltage. Thereafter, the voltage on the word line W
1
is set to a value between the two threshold voltages. In this case, if the ferroelectric film
3
of the ferroelectric FET M
11
has the low threshold voltage, i.e., the logical state of the ferroelectric FET M
11
is “1”, the ferroelectric FET M
11
is ON state and a current flows from the source line S
1
toward the bit line B
1
. Thus, the bit line B
1
is charged and the voltage on the bit line B
1
rises. On the other hand, if the ferroelectric film
3
of the ferroelectric FET M
11
has the high threshold voltage, i.e., the logical state of the ferroelectric FET M
11
is “0”, then the ferroelectric FET M
11
is OFF state. Thus, the bit line B
1
is not charged and the voltage on the bit line B
1
remains low. Accordingly, it is possible to know the logical state retained on the memory cell depending on whether the voltage on the bit line B
1
is high or low.
However, if a voltage is applied to the word line every time data is read out, the ferroelectric film of a ferroelectric FET in “0” state will be supplied with voltages gradually approaching “1” state even where the voltage is an intermediate value between the two threshold voltages that determine the polarization states of the ferroelectric film. As a result, the “0”-state ferroelectric film, connected to the word line through which the read voltage is applied, gradually makes a transition to “1” state every time a read operation is performed. Thus, there is a problem that a disturb phenomenon occurs, i.e., it becomes more and more difficult to tell “0” from “1”.
To avoid this problem, the ferroelectric FET is made to operate either in enhancement mode or depletion mode in accordance with the polarization state of the ferroelectric film, and the enhancement and depletion modes are associated with the two logical levels. Then, it is possible to read data with no voltage applied onto the word line.
However, the depletion mode ferroelectric FET is always “1”, i.e., normally ON, even when the gate voltage is zero. Accordingly if the logical state retained on a non-selected memory cell is “1”, a path for a current flowing from a bit line to a source line is formed by way of the non-selected memory cell. As a result, there occurs a problem that a voltage on the bit line is variable depending on the state of the non-selected memory cell.
For that reason, as disclosed in Japanese Laid-Open Publication No. 8-139286, select transistors need to be disposed between a selected memory cell and a word line and between the memory cell and a bit line, respectively. Accordingly, there occurs another problem that the number of devices making up a memory cell increases.
That is to say, if such ferroelectric FETs are arranged in matrix, the select transistors are needed between each memory cell and an associated word line and between the cell and an associated bit line. Further, a substrate for a ferroelectric FET in each memory cell should be electrically isolated at least from a substrate for a ferroelectric FET in another memory cell which is connected to an adjacent word or bit line, with a well region interposed between them. Otherwise, a selective write operation cannot be performed. As a result, the size of the memory cell unintentionally increases, typically several times as large as a memory cell with one transistor and one capacitor.
DISCLOSURE OF INVENTION
It is therefore an object of the present invention to solve the above-mentioned problems, i.e., to eliminate the disturb phenomenon when data is read out and to reduce the area of a memory cell by having the memory cell constructed of a smaller number of devices.
To achieve this object, a semiconductor memory device according to the present invention includes: source/drain regions for a field effect transistor, the source/drain regions being defined in a semiconductor substrate with a channel region interposed therebetween; an insulating film formed on the semiconductor substrate; a first gate electrode which is formed on the insulating film and has a gate length shorter than the length of the channel region; a ferroelectric film formed to cover the first gate electrode and to have both side portions thereof make contact with the insulating film; and a second gate electrode formed to cover the ferroelectric film.
In the semiconductor memory device according to the present invention, when data is read out, the polarization in the ferroelectric film, which determines continuous or discontinuous state of the channel region, is not affected even if a positive voltage is applied to the first gate electrode with the semiconductor substrate and second gate electrode grounded. Thus, during the read operation, the polarization does n

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