Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-11-27
2002-04-16
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S781000, C257S784000, C257S792000
Reexamination Certificate
active
06373128
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to microelectronic assemblies, and more specifically it relates to arrangements facilitating connection between a microelectronic component such as a semiconductor chip and external circuit elements.
BACKGROUND OF THE INVENTION
Semiconductor chips or integrated circuits are typically used in combination with such elements as interposers and substrates facilitating connection between the chip itself and the external circuit elements. The entire circuit operation depends upon the connections between the chip, the interposer and the substrate.
Various attempts have been made to produce connections between the chip and the external elements satisfying the above discussed requirements. In this respect, U.S. Pat. No. 5,148,265, granted Sep. 15, 1992, the disclosure of which is hereby incorporated by reference, discloses an advanced method for providing the connection between a semiconductor chip and external circuit elements. According to certain embodiments discussed in this patent, a semiconductor chip is connected to a corresponding substrate through a dielectric interposer. The semiconductor chip has a plurality of peripheral contacts positioned in a peripheral area of a front surface thereof. The flat, flexible interposer is formed with a plurality of connecting terminals, each of which is connected to a bonding terminal adjacent the periphery of the interposer. The flexible interposer is supported by a compliant layer. The peripheral contacts of the semiconductor chip are connected to the terminals of the interposer by bonding a multiplicity of fine wires between the bonding terminals and the contacts of the chip.
During the wire bonding operation, when the downwardly directed forces are applied to the peripheral region of the interposer containing the bonding terminals this area of the interposer flexes downwardly. This impedes the bonding of the wires and the bonding terminals.
Thus, further improvement would be desirable.
SUMMARY OF THE INVENTION
One aspect of the invention provides a microelectronic assembly comprising an interposer including a top layer with oppositely facing first and second surfaces. The top layer includes a connecting terminal region and a bonding terminal region. The interposer has connecting terminals on the second surface in the connecting terminal region and has bonding terminals in the bonding terminal region. The assembly also includes a microelectronic element such as a semiconductor chip or other element having a front surface and having contacts on the front surface. The interposer top layer overlies the front surface with said second surface facing upwardly away from the chip and with said first surface facing downwardly toward the microelectronic element. The connecting terminals are movable relative to said microelectronic element in vertical directions, towards the microelectronic element, whereas the bonding terminals are supported against such vertical movement.
The top layer preferably is a thin, flexible layer, and the assembly preferably includes a compliant layer disposed between the top layer and the microelectronic element and movably supporting the connecting terminal region of the top layer. The assembly according to this aspect of the invention desirably also includes means for reinforcing the bonding terminal region of said top layer against vertical movement towards said microelectronic element. Subassemblies according to this aspect of the invention can be subjected to a bonding operation, such as a wire bonding operation, in which flexible conductors such as bonding wires are connected between the bonding terminals and the contacts on the chip. Because the bonding terminal region is reinforced, the bonding operation can be conducted efficiently. However, the finished assembly still provides the benefits associated with a compliantly mounted interposer, including testability and compensation for thermal effects during service.
Alternatively, the interposer top layer bearing the connecting and bonding terminals may or may not include a rigid portion in the binding terminal region and a more flexible portion in the connecting terminal region. Here again, the top layer may be supported by a compliant layer between the top layer and the microelectronic element. In this arrangement, the rigid top layer spreads loads applied to individual bonding terminals over a large area of the compliant layer, and thus reinforces each bonding terminal against downward movement during the connecting step.
According to a further aspect of the invention, a semiconductor chip assembly is provided having a semiconductor chip with a front surface defining the top of the chip. The front surface includes a peripheral region. A plurality of peripheral contacts of the chip are disposed in the peripheral region of the front surface. A generally planar interposer overlies the front surface of the chip, the interposer having a first surface facing towards the chip and a second surface facing away from the chip. A peripheral region of the interposer is disposed adjacent the edges thereof. A plurality of connecting terminals are disposed on the interposer. The connecting terminals face away from the chip and are exposed at the second surface of the interposer for connection to another component such as a substrate. Each connecting terminal is electrically connected to a bonding terminal situated in the peripheral region of the interposer, on the second surface thereof. At least some of the peripheral contacts and at least some of the bonding terminals are connected by movable peripheral contact leads. A support structure reinforces the peripheral region of the interposer facilitating connection between the peripheral contact leads and the central terminals. the support structure may be in the form of a ring encircling an interior area which may be substantially empty. The peripheral region of the interposer and the bonding terminals are reinforced by the support structure,
A central part of the interposer corresponding to the interior area of the support structure preferably is movable in a vertical direction to permit vertical movement of the connecting terminals relative to the chip. Thus, the interior area within the support structure underlying the central region of the interposer may contain a layer of a compliant material such as a gel or elastomer, which supports the central region of the interposer. As further discussed herein, such movability facilitates connection and testing of the assembly. The support structure can be independent from the interposer or can form a part of the interposer.
The support structure may project vertically from the first surface of the interposer in the peripheral region thereof. A plurality of grooves can be provided extending horizontally across the support structure. Such grooves desirably connect the interior area with an area outside the support structure. As discussed herein, these grooves facilitate introduction of the compliant material to the interior area.
A still further aspect of the present invention provides a method of forming a microelectronic assembly such as a semiconductor chip assembly consisting of an element having a front surface thereof and an interposer having connecting terminals in a connecting terminal region and bonding terminals in a bonding terminal region. The method includes the step of placing the interposer on the element so that the connecting terminals and the bonding terminals of the interposer face away from the front surface of the element. The method further includes the step of connecting at least some of the contacts on the element with at least some of the bonding terminals by attaching flexible leads such as bonding wires, while supporting at least the bonding terminal region of the interposer and the bonding terminals in the vertical direction to facilitate the connection.
The method may further include the step of testing, wherein the semiconductor assembly is tested by a testing arrangement having a plurality of
Fjelstad Joseph
Karavakis Konstantine
Clark Jhihan B
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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