Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2000-02-12
2002-03-12
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S189070, C365S222000
Reexamination Certificate
active
06356485
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to the writing of those memories incorporating a write queue.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
Over the years various capabilities have been included on many circuits incorporating dynamic memory arrays to lessen the difficulty of dealing with the refresh requirements of the dynamic memory cells. On-chip refresh counters are frequently used to store a refresh address, which is used during a refresh cycle (rather than the externally provided address) to access the next row requiring refreshing, after which the refresh address is usually incremented in preparation for the next refresh cycle. These on-chip counters are helpful, even if a refresh cycle is controlled by an external clock signal, because the address path from the system need not include the delay and complexity of a multiplexer to switch between the system memory address and a refresh address. Self-refresh timing control circuits are sometimes included to automatically determine when a refresh cycle should be performed, and to automatically initiate such a cycle if the memory is not already occupied in carrying out an external memory cycle request. At one time, the asynchronous arbitration between an external cycle request and an internal refresh cycle request was worrisome because of potential meta-stability concerns, but more recently, with the increasing popularity of synchronous memories, such control circuits are also synchronous and meta-stability problems in determining what kind of cycle to initiate are largely eliminated.
One problem, however, that remains a concern for system designers is ensuring, over all possible system memory operations and address sequences, that enough time is available for sufficient refresh cycles. That is, even if the refresh control is totally handled on-chip, the memory (or portions of the memory) must be “idle” at least often enough to allow an occasional refresh cycle to execute. When this cannot be assured, the memory frequently must intercede over system accesses and take the necessary time to perform the refresh cycle, thus interrupting or at least delaying (e.g., wait states) normal access to the memory. Such delays degrade system efficiency and performance. Consequently, continued improvements are still desired.
In addition, at ever increasing frequencies of operation, and with more and more portable battery operated equipment is use, power dissipation is becoming ever more important. There is a continuing need to reduce power consumption wherever possible.
SUMMARY OF THE INVENTION
In an integrated circuit incorporating a write queue, the address (or a portion thereof) of a given external write cycle may be stored and compared to the address of a subsequent external write cycle. If the selected memory cells to be written in both external write cycles correspond to the same physical word line and the same column within the same array block of the same memory bank, the internal write operation which would otherwise follow from the first external write cycle is delayed, and the data to be written is queued and merged with the data to be written in the subsequent external write cycle. The write queue then “retires” both queued write requests by performing a single internal write operation, simultaneously writing both data words received in the two external write cycles. Such a “merging” of write cycles keeps the ultimately selected memory bank inactive during the “merged” cycle, which allows a hidden refresh cycle to occur in the selected memory bank during the “merged” cycle. Moreover, a significant amount of internal power consumption is saved compared to performing two separate write operations since the selected memory bank is cycled only once (instead of twice) to write the two words. This is particularly attractive when accessing the memory using sequential addresses, as would frequently occur during a burst mode access or when accessing a contiguous block of data, such as a cache line fill operation for a processor. Such sequentially-addressed consecutive write cycles may be merged even if a non-write cycle occurs between the two consecutive write cycles (i.e., the consecutive write cycles need not be consecutive cycles). Moreover, other kinds of memory arrays, particularly static memory arrays, also can benefit greatly from the power saved by merging write cycles and performing one write operation instead of two. Any write-able memory array already incorporating a write queue, or to which a write queue may be added, can benefit from this invention.
In an exemplary embodiment of the present invention, a dynamic memory array includes an internal data path to and from the array that is twice as wide as the external I/O word width. A 72-bit internal data path conveys two 36-bit words, selected by the least significant address bit. If the internal data path were wider than two 36-bit words, then more than two 36-bit write cycles could be merged into a single internal write operation. For example, if the internal data path were 144-bits wide, then four 36-bit write cycles could be merged into a single internal write operation. Moreover, there is no reason to limit cycle merging at just two consecutive cycles. As an additional example, four sequential external write cycles, each writing a different (or over-writing the same) 9-bit byte within a 36-bit word corresponding to a given address, followed by four more sequential external write cycles, each writing a different (or over-writing the same) 9-bit byte within a 36-bit word at an address which differs from the given address only in the LSB, may be carried out internally as a single internal write operation, simultaneously writing all 72-bits (assuming all 8 bytes were byte-write enabled in at least one of the eight cycles) into the selected memory cells.
In a broader embodiment of the present invention, an integrated circuit includes a memory array including a plurality of memory cells, a write queue circuit for storing address information and data for at least one pending internal write operation into the memory array, and a write decision circuit for determining whether a first group of memory cells to be otherwise written by a pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using
Integrated Device Technology Inc.
Le Vu A.
Nguyen Tuan T.
Zagorin O'Brien Graham LLP
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