Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-06-26
2002-08-13
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230030
Reexamination Certificate
active
06434064
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device comprising a redundancy circuit for saving a faulty memory cell.
2. Description of the Related Art
In a semiconductor memory device, in the case where a faulty memory cell has been detected, there is adopted a redundancy circuit system (redundancy system) in which the faulty memory cell is replaced with a redundancy cell, that is, a redundancy cell is used in place of a faulty memory cell, thereby improving the yield of the semiconductor storage device. Currently, in a generally employed redundancy system, one or plural rows of memory cell arrays or one or plural columns are defined as a replacement unit (namely, a saving unit). The replacement unit of memory cells including a faulty memory cell, in a sub-block called a saving block unit for saving such faulty memory cells is replaced with a redundancy saving unit (spare element) having the same size. In the case where a faulty sub-block containing such faulty memory cell has been detected, a spare element is used in place of such faulty cell block.
In order to store an address information of a replacement unit containing a faulty memory cell, it is required to employ a nonvolatile storage element. Currently, a fuse is generally used. Address information is generally composed of a plurality of bits, and thus, a fuse set of plural fuses that correspond to such plurality of bits becomes a unit of storage of address information on one sub-block. In general, the number of spare elements corresponds to that of fuse sets one by one, and thus, the fuse sets whose number is the same as that of spare elements are arranged in a memory chip. In the case of using such spare element, the fuse in the fuse sets that correspond to the spare elements is disconnected according to address information on a faulty cell. This system is simple in configuration, and is currently widely used.
In a semiconductor memory, memory cells are arranged in a planar (two dimensional) manner. Currently, it is well known to store “0” or “1” bit information in one memory cell. As address information for designating one memory cell, there are used two addresses, row address and column address. That is, two coordinates, i.e., an X-coordinate (row address) and a Y-coordinate (column address) are used in order to designate one memory cell. In order to save a faulty memory cell, two circuits, i.e., a row redundancy circuit and a column redundancy circuit are mounted so as to use any of a method for saving the faulty memory cell with a row spare element and a method for saving the faulty memory cell with a column spare element. However, the number of faults that can be saved with the row spare element is independent of the number of faults that can be saved with the column spare element.
As described above, a redundancy system requires a redundancy circuit such as spare element and fuse set. In a conventional redundancy system in which the spare element corresponds to the fuse set in number one by one, the number of fuse sets increases with an increased number of spare elements, and a memory chip area also increases. In this case, the fuse set generally requires a larger area than the spare element, and thus, the area efficiency of the redundancy circuit is significantly lowered.
In order to solve this problem, there are proposed a variety of redundancy systems that improve the area efficiency of the redundancy circuit. For example, there is known a flexible redundancy system (refer to “Fault-Tolerant Design for 256 Mb DRAM” (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, No. 4, April 1996) proposed by Kirihata et al. for example. In this system, one spare element covers a wide cell array region. Thus, even in the case where faulty cells locally, i.e. collectively, exist at a portion of a memory chip, such faulty cells can be saved in a manner similar to a case in which faults are distributed uniformly in a cell array. Because of this, this system reduces the number of spare elements, whereby the area efficiency of the redundancy circuit can be improved. In addition, this system is effective in the case where the average number of faulty cells per memory chip is identified or can be predicted.
On the other hand, in recent years, there has been developed a memory chip on which a memory cell array is divided into a plurality of sections. For example, there is a memory chip having a plurality of banks, wherein these banks are activated at the same time. In such a memory chip, it is impossible to use a row spare element in a bank, for saving faulty memory cells in units of rows as a row spare element in another bank. Thus, a spare element is unavoidably provided for each bank. More banks increase the number of divisions in memory cell arrays in a memory chip, and thus, one spare element can cover only a small cell array area. Even in the case where the spare element can cover only such small cell array region or even in the case where faults locally exist at a portion of a memory cell array, the spare element must be provided for such each small cell array region in order to save faulty cells. Therefore, the total number of spare elements significantly increases, resulting in a significant increase in required memory chip area. That is, in view of the entire memory chip, the number of spare elements that significantly exceeds the average number of faulty cells per memory chip is incorporated in one memory chip, and thus, the area efficiency of the memory chip is degraded.
In addition, in a semiconductor memory device required to transfer a large amount of data at one time due to the pursuit of high speed, a column is divided in fine units. Thus, a column spare element for saving a faulty memory cell in units of columns is unavoidably provided for each column unit. Therefore, the area efficiency of the memory chip is significantly lowered.
In view of such a circumstance, there has been proposed a flexible mapping redundancy technique in which the number of fuse sets that exceeds the assumed number of faulty cells in the entire cell array is reduced to be smaller than the total number of spare elements in a semiconductor memory device disclosed in S. Takase et al., “A 1.6-Gbyte/s DRAN with Flexible Mapping Redundancy Technique and Additional Refresh Scheme” IEEE JSSC, VOL 34, No. 11, pp. 1600-1605, November, 1999 and U.S. Pat. No. 6,188,618.
In the flexible mapping redundancy of the semiconductor memory device disclosed in U.S. Pat. No. 6,188,618, a plurality of spare elements for replacing faulty cells are arranged in a memory cell array contained in a memory chip. A fuse set contains a faulty address. The fuse set also contains mapping information indicating a correspondence between the fuse set and a spare element. In the case where a faulty address coincides with an input address, a signal for activating the corresponding spare element is outputted. There is no need to associate each fuse set with a spare element one by one.
Hereinafter, a flexible mapping redundancy technique disclosed in U.S. Pat. No. 6,188,618 will be briefly described with reference to matters related to the present invention.
In a memory cell array of the semiconductor memory device, a plurality of spare elements for saving faulty cells are disposed in a memory chip, and there are fuse sets fewer than the total number of spare elements. These fuse sets each contain a faulty address and mapping information indicating a correspondence between and the fuse set and the spare element. In the case where a faulty address coincides with an input address, an arrangement is provided so as to output a signal for activating the corresponding spare element.
FIG. 12
schematically shows a configuration of a fuse set that contains the mapping information. In a fuse set shown in
FIG. 12
, a fail address detector circuit (Fail Address Detector)
121
receives an address acquisition signal “strb”. In the case where an input
Banner & Witcoff , Ltd.
Ho Hoai
Kabushiki Kaisha Toshiba
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