Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-21
2002-09-17
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S353000, C257S354000
Reexamination Certificate
active
06452233
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device using an SOI substrate having an SOI (Silicon On Insulator) structure in which a buried oxidation film and a surface silicon layer are provided on a support substrate made of silicon and a method of fabricating the same.
2. Description of the Related Art
The SOI substrate is a semiconductor substrate where a surface silicon layer is formed above a support substrate made of silicon with a buried oxidation film therebetween. The semiconductor device fabricated using such SOI substrate has a lot of advantages compared with a semiconductor device fabricated with bulk silicon. For instance, these advantages are that the semiconductor device with the SOI substrate has high resistance to temperature and radiation, capability of realizing quick operation with ease, low power consumption, and so on.
Hereinafter, an example of a semiconductor device using a conventional SOI substrate will be described with FIG.
13
.
FIG. 13
is a sectional view showing the enlarged principal portion of an IC chip that is the semiconductor device using the conventional SOI substrate.
In an SOI substrate
1
, a buried oxidation film
19
is provided on a support substrate
17
made of silicon and a surface silicon layer is provided on the buried oxidation film
19
. However, in
FIG. 13
, the surface silicon layer is etched to form a plurality of island-shaped component regions and impurities are implanted into each component region and diffused to form a lightly doped P region
3
and a lightly doped N region
4
.
An N channel field effect transistor (hereinafter referred to as “an N channel FET”)
20
and a P channel field effect transistor (hereinafter referred to as “a P channel FET”)
30
are provided respectively on the lightly doped P region
3
and the lightly doped N region
4
isolated from each other by an insulating film
23
.
In the N channel FET
20
, a gate electrode
21
is formed above the center of the lightly doped P region
3
with a gate oxidation film
15
therebetween, and an N source region
7
and an N drain region
5
are formed respectively on both sides of the gate electrode
21
. The gate electrode
21
, the N source region
7
, and the N drain region
5
are respectively provided with metal electrodes (interconnection electrodes)
11
electrically connected thereto and extending onto the insulating film
23
through contact holes
31
.
In the P channel FET
30
, a gate electrode
21
is formed above the center of the lightly doped N region
4
with a gate oxidation film
15
therebetween, and a P source region
27
and a P drain region
25
are formed respectively on both sides of the gate electrode
21
. The gate electrode
21
, the P source region
27
, and the P drain region
25
are also respectively provided with metal electrodes (interconnection electrodes)
11
electrically connected thereto and extending onto the insulating film
23
through contact holes
31
.
Incidentally, since the metal electrodes (interconnection electrodes) connecting with the gate electrodes
21
of the N channel FET
20
and the P channel FET
30
are respectively provided at positions in a section different from
FIG. 13
, they are not shown in FIG.
13
. Moreover, pad portions for providing input/output terminals are formed at the metal electrodes
11
connecting with the outside out of a number of metal electrodes
11
, though the illustration thereof is omitted.
The N channel FET
20
and the P channel FET
30
are merely inverse in conduction type of the lightly doped region, the source region, and the drain region, and they have a common basic structure. The pair of N channel FET
20
and P channel FET
30
constitute a CMOS transistor.
In
FIG. 13
, only one pair of CMOS transistors is shown, but a number of CMOS transistors, other FETs, bipolar transistors, resistors, or capacitors are provided in an actual IC chip. All of these are, of course, made by the SOI technology.
When the IC chip which is the semiconductor device using the aforesaid SOI substrate is operated, it is necessary to ground or bias the support substrate at a predetermined voltage. Thereby, the operation of the IC chip can be stabilized.
However, in the case where the IC chip in which the CMOS transistor is formed on the SOI substrate as shown in
FIG. 13
is driven, the support substrate
17
made of silicon is grounded or biased, which causes the following disadvantage.
In one of the FETs composing the CMOS transistor, the support substrate
17
comes to be different in potential from the lightly doped P region
3
or the lightly doped N region
4
which are formed out of the surface silicon layer. For instance, as shown in
FIG. 13
, when the support substrate is set at the ground potential, the lightly doped P region
3
of the N channel FET
20
is set at the ground potential but the lightly doped N region
4
of the P channel FET
30
must be set at a power source potential (by an applied voltage VDD). Therefore, a potential difference is caused between the lightly doped N region
4
and the support substrate
17
.
So, the disadvantage due to an occurrence of such potential difference will be explained with reference to FIG.
14
and
FIG. 15
showing an enlarged portion of only one P channel FET
30
in FIG.
13
. Incidentally, in the sectional views, part of the hatching is omitted for convenience of illustration.
The lightly doped N region
4
and the P source region
27
in
FIG. 14
form a PN junction, normally the P source region
27
is set at the power source potential, and carriers come into recombination in the lightly doped N region
4
near a boundary surface between the lightly doped N region
4
and the P source region
27
, whereby a depletion layer
34
is formed as shown in the drawing.
If the value of the voltage VDD applied to the lightly doped region
4
is changed to the positive voltage side, electrons in the lightly doped N region
4
near a boundary surface
39
between the lightly doped N region
4
and the buried oxidation side
19
are excluded, whereby a depletion layer
35
is formed. When the applied voltage VDD becomes about
5
V, an inversion layer
36
composed of holes is formed near the boundary surface
39
and the depletion layer
35
growing from the buried oxidation
19
side and the depletion layer
34
growing from the P source region
27
are joined finally.
At this time, the potential difference between the support substrate
17
and the lightly doped N region
4
comes to directly exert on the PN junction formed at the boundary surface between the lightly doped N region
4
and the P source region
27
, and thus the potential barrier of the PN junction is lowered, whereby carriers (holes)
37
are supplied from the P source region
27
to the inversion layer
36
as shown by an arrow a in FIG.
15
.
On the other hand, since the P drain region
25
is normally applied with a drain voltage Vd with which the P drain region
25
is reverse-biased in relation to the lightly doped N region
4
, the carriers (holes)
37
flow from the inversion layer
36
into the P drain region
25
as shown by an arrow c. Consequently, a leakage current appears along the boundary surface
39
as shown by an arrow b, resulting in the formation of a path of current in addition to the channel current. When the leakage current appears as described above, a current flows even when no voltage is applied to the gate electrode
21
, whereby the current flowing in the channel cannot be controlled accurately by the voltage applied to the gate electrode
21
.
In other words, there is a disadvantage that a leakage current flowing along the boundary surface
39
between the lightly doped N region
4
and the buried oxidation film
19
appears due to the potential difference between the voltage VDD applied to the lightly doped N region
4
and the support substrate
17
, resulting in inaccurate control of the channel current.
It is possible that the above disadvantage arises not only in the P
Armstrong Westerman & Hattori, LLP
Citizen Watch Co. Ltd.
Eckert II George C.
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