Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2001-01-03
2002-05-28
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S784000, C257S750000, C257S758000, C257S693000
Reexamination Certificate
active
06396157
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device which is assembled and installed in an electronic apparatus, and also concerns a manufacturing method of such a device.
BACKGROUND OF THE INVENTION
Conventionally, with respect to semiconductor integrated circuit devices including semiconductor integrated circuit chips (hereinafter, referred to as IC chips), various external shapes have been proposed from the viewpoints of functions, purposes of use and assembling properties onto printed substrates of IC chips.
In recent years, particularly, in the field of small-size portable apparatuses, there has been an ever-increasing demand for further miniaturized semiconductor integrated circuit devices so as to satisfy the need of high-density assembling properties of electronic parts installed therein. Such miniaturized semiconductor integrated circuit devices are referred to as CSP (Chip Size Package or Chip Scale Package). With respect to externally connecting terminals of the CSP, solder balls, arranged in a matrix format, have been generally used.
FIG.
6
(
a
) is a plan view that shows a structural example of a conventional semiconductor integrated circuit. FIG.
6
(
b
) is a cross-sectional view taken along D—D of FIG.
6
(
a
). This semiconductor integrated circuit device
101
is constituted by an IC chip
102
, a plurality of first electrode pads
103
, a first insulating layer
104
, a plurality of wires (redistribution)
105
, a plurality of second electrode pads
106
, a second insulation layer
107
and a plurality of externally connecting terminals
108
.
A plurality of electrode pads
103
are formed on the surface of the IC chip
2
. The first insulation layer
104
is stacked on the IC chip
102
in such a manner that at least one portion of each of the electrode pads
103
is exposed. The wires (redistribution)
105
are placed so as to allow the first electrode pads
103
to be electrically connected to the respective second electrode pads
106
. The second insulation layer
107
is stacked on the IC chip
102
with at least one portion of the second electrode pads
106
being exposed. The externally connecting terminals
108
are formed by solder balls and placed on the respective second electrode pads
106
.
The semiconductor integrated circuit device
101
having the above-mentioned structure, together with other semiconductor integrated circuit devices (CSP), has been proposed in featuring articles Part 1 and Part 2 (pages 42 to 59) of “Nikkei Microdevice 1998-8 (August 1 issue)” published by Nikkei BP Ltd.
In accordance with this article, in the formation method of the portion corresponding to the wires
105
, first, a polymer passivation film (corresponding to the first insulation layer
104
) is formed, and wires are formed on this film. FIGS.
7
(
a
) through
7
(
e
) are drawings that show processes in which the portion of the above-mentioned wires
105
is formed by using the above-mentioned generally-used method. Here, in this state, the semiconductor integrated circuit devices
101
are formed on a wafer, and have not been divided into individual semiconductor integrated circuits.
First, a wiring base metal
109
, which forms a base layer of the wires
105
, is formed on the entire surface (the entire surface of the IC chip
102
) of a wafer by sputtering (see FIG.
7
(
a
)). Next, photoresist
110
is applied onto this layer (see FIG.
7
(
b
)), and this is subjected to exposure and development so that the photoresist
110
placed on the formation area of the wiring
105
is removed (see FIG.
7
(
c
)). Moreover, wires
105
are formed on portions from which the photoresist
110
has been removed, by plating, etc. (see FIG.
7
(
d
)). After formation of the wires
105
, all the photoresist
110
is removed, the wiring base metal
109
located between the wires
105
is etched by chemical, etc., and the second insulation layer
107
and the externally connecting terminal
108
are then formed (see FIG.
7
(
e
)). Through these processes, the respective wires
105
are formed as an electrically isolated pattern.
Moreover, in addition to the above-mentioned formation method, another method has been proposed in which conductive paste is simply printed by using a mask formed by etching a steel plate or a meshed screen mask so as to form wires.
However, in the above-mentioned method, in an attempt to form wires (redistribution)
105
inside the conventional semiconductor circuit device by using a method having the same basic principle as a technique referred to as a photolithography method for forming fine circuits of an IC chip, the following seven processes are required.
(1) Process for forming the wiring base metal by sputtering
(2) Application of photoresist
(3) Process for exposing the photoresist
(4) Process for developing the photoresist
(5) Process for plating wiring (redistribution) material
(6) Process for removing the photoresist
(7) Process for etching the wiring (redistribution) base metal
In the above-mentioned conventional method, the above-mentioned many (seven) processes are required because of the structure in which the wires
105
are distributed on the insulation layer
104
. Each of these processes requires an exclusively-used device; therefore, if there is any process that can be omitted from the above-mentioned seven processes or if there is another process that can replace any of the processes so as to reduce the production cost, without causing degradation in the functions of the wires
105
, the above-mentioned seven processes will cause extra costs that would be reduced by such a process to be omitted or to be replaced with.
On the other hand, in the case when the wires
105
are formed by simply printing conductive paste by using a mask formed by etching a steel plate or a meshed screen mask, the following problems arise.
(1) A problem in which after removing the mask, the conductive paste tends to spread in the horizontal direction.
(2) A problem in which, taking into consideration the present mask processing technique (with respect to masks formed by etching steel plates, meshed screen masks, etc.), it is difficult to form wires not more than 50 &mgr;m in a stable manner (without contact between the adjacent wires, without discontinuity in the wires).
In the semiconductor integrated circuit device
101
, a plurality of the wires
105
are arranged so as to pass between the externally connecting terminals
108
; therefore, it is not possible to narrow the distance between the externally connecting terminals
108
without the fine processing. Consequently, in the case when such a method is used, it is inevitable to design the semiconductor integrated circuit device
101
to have a large size.
Japanese Laid-Open Patent Application No. 264932/1996 “Tokukaihei 8-264932 (published on Oct. 11, 1996)” has disclosed a formation method of solder bumps in which, at the time of forming solder bumps, solder is not transferred so that it is possible to prevent degradation in forming the solder balls (see FIGS.
8
(
a
) through
8
(
e
)).
In other words, in accordance with the method disclosed in the above-mentioned patent publication, prior to the printing process, a spacers
112
is placed on a printed wiring board
111
, and then affixed thereon (see FIG.
8
(
a
)) Further, the metal mask
113
is fitted to spacer
112
(see FIG.
8
(
b
)). Then, paste
114
is put on the metal mask
113
, and the solder paste
114
is filled in opening sections
116
, and printed therein (see FIG.
8
(
b
)), by using a normal screen printing method while a stage
115
being shifted from right to left as shown by arrow P (see FIG.
8
(
b
)). Next, the metal mask
113
is removed from the spacer
112
, and heated by using a reflow device (see FIG.
8
(
c
)). Then, the solder paste
114
is allowed to form a spherical shape through surface tension (see FIG.
8
(
d
)). In this state, this is cooled and the spacer
112
is removed from the printed wiring board
111
so that solder bumps
117
are formed on the pri
Ishio Toshiya
Mori Katsunobu
Nakanishi Hiroyuki
Suminoe Shinji
Clark Jhihan B
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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