Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-11
2002-08-13
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000
Reexamination Certificate
active
06433393
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor protective device, and to a method of manufacturing a semiconductor protective device.
More particularly, it relates to an on-chip static electricity protective element in a semiconductor device comprising a fine-featured complimentary MOS semiconductor integrated circuit having a minimum interconnect width of 0.5 micron or less.
DESCRIPTION OF THE RELATED ART
In the past, a semiconductor on-chip static electricity protective technology of this type has been known to persons skilled in the art, from the following literature, for example.
More specifically, as shown in
FIG. 6
, the U.S. Pat. No. 5,502,317 has a disclosure of an N well
142
formed on the surface of a P-type semiconductor substrate
126
, a P-type diffusion layer
146
and N-type diffusion layer
144
connected to an external terminal formed therein, and N-type diffusion layer
114
formed on a semiconductor substrate
126
part of which is included in the N well
142
, an N-type diffusion layer
112
connected to a ground terminal
118
and an N-type diffusion layer
122
formed on the semiconductor substrate
126
, via an element separation region
124
.
In this known semiconductor protective device, when an excessive positive static electricity voltage is applied to the external terminal, the PN junction formed by the N-type diffusion layer
114
and the P-type semiconductor substrate
126
exhibits an avalanche breakdown, thereby raising the potential on the substrate.
Because of this action, the NPN transistor formed by the N-type diffusion layer
114
, the P-type semiconductor substrate
126
, and the N-type diffusion layer
112
conducts.
Because of this, the potential in the region of the P-type diffusion layer
146
of the N well
142
decreases, so that the PNP transistor formed by the P-type diffusion layer
146
, the N well
142
, and the P-type semiconductor substrate
126
conducts.
As a result, the NPN transistor and PNP transistor operate in a complimentary manner so as to enhance the collector current, the result being entry into the low-resistance condition of so-called thyristor operation, thereby enabling protection of the internal circuit by causing a current to flow.
In the U.S. Pat. No. 5,872,379, which is a similar example of prior art, as shown in
FIG. 7
, the basic configuration is the same as shown in
FIG. 6
, the major difference between FIG.
6
and
FIG. 7
configurations being that, in place of the element separation region
124
shown in
FIG. 6
, in
FIG. 7
a P-type diffusion layer
38
having a P-LDD structure is formed, the reverse withstand voltage of the PN junction at the boundary
40
between the P-type diffusion layer
38
and the N-type diffusion layer
20
being decreased, so that the trigger voltage for thyristor operation is lowered, thereby improving the protective capacity.
This type of semiconductor protective element of the past is effective with respect to an external pulse having a slow rise time. However, it is poor in protective capacity with respect to a pulse having a fast rise time.
In particular, there is a known charged device model (CDM) mode static pulse in which the rise time is extremely fast, this being 500 ps or shorter, and having a large discharge current of 10 A or more, thereby causing failures of the gate oxide film or the like in a fine-featured MOS LSI element. The protective element of the past is particularly troubled with a low capacity to provide protection for such fast mode static pulses as these.
By various simulations, the inventors, as a result of an investigation of the cause of the low protective capacity of this type of protective element with respect to a CDM mode pulse, were able to discover the cause thereof.
Specifically, there are two causes, which differ depending upon whether the overvoltage is positive or negative.
For example, in the first case, in which a positive overvoltage is applied to a semiconductor protective element of this type from the prior art, the element operates as a thyristor, but the starting speed is slow, so that a voltage greater than the breakdown voltage is applied to the internal circuit, thereby causing a low breakdown withstand voltage with respect to a fast pulse.
Additionally, in accordance with the simulations performed by the inventors, it was discovered that the starting speed is dependent upon the distance Dac between the anode and the cathode electrodes of the thyristor element.
Specifically,
FIG. 10
shows the results of a simulation for the case in which a thyristor element of the past is used as a protective element, with a CDM mode static electricity pulse of 1000 V applied, in which the relationship between the voltage VoxMAX applied to the internal circuitry to be protected and the distance Dac between the anode and cathode of the thyristor element is shown.
As is clear from
FIG. 10
, to reduce the maximum voltage VoxMAX applied to the internal circuit, it is necessary to reduce the distance Dac between the anode electrode and the cathode electrode of the thyristor element.
However, it was difficult to reduce this distance with the structure of the past. That is, in
FIG. 6
, which shows the configuration of prior art as disclosed in the U.S. Pat. No. 5,502,317, the reference numeral
146
denotes the anode electrode and
112
denotes the cathode electrode, there being an N-type diffusion layer
114
and element separation film
124
therebetween, which restricts the reduction of the anode-to-cathode distance Dac.
In
FIG. 7
, which shows the configuration of the specification of the U.S. Pat. No. 5,872,379 which discloses prior art, the reference numeral
34
denotes the anode electrode and
18
denotes the cathode electrode, between which are interposed an N-type diffusion layer
20
and a P-type diffusion layer
38
, which make reduction of Dac difficult.
The second case is that in which a negative CDM mode pulse is applied to a protective element of the past. The reason for a reduction in protective capacity in this case is that the element operates as a diode, wherein parasitic resistance of the element causes a rise in the voltage of the circuit to be protected.
That is, in the case of a CDM mode static discharge, because of the large discharge current, with even a small parasitic resistance, there is a rise in the voltage generated at the element terminals, thereby causing breakdown of the internal circuit.
The inventors discovered by their simulations that the parasitic resistance is substantially proportional to the distance between the diode cathode and anode. It is therefore desirable to reduce the distance between the cathode and the anode of the diode, although this was difficult to achieve in the structure of the past.
Specifically, in the structure disclosed in U.S. Pat. No. 5,872,379, for diode operation, the N-type diffusion layer
20
acts as the cathode electrode and the P-type diffusion layer
14
acts as the anode electrode, with an N-type electrode
18
and a P-type electrode
38
interposed therebetween, so that there is a limitation on the reduction of the distance therebetween that can be achieved.
Additionally, in Japanese Patent No. 2669245, there is disclosure of a configuration which uses a junction-type field effect transistor as a protective element.
However, there is no language therein with regard to technology for using a protective circuit having a thyristor structure with respect to CDM mode static discharge in a fine-featured semiconductor device.
Additionally, in the Japanese Unexamined Patent Publication (KOKAI) No. 59-181044, there is disclosure of a configuration which uses a protective circuit having two diode and resistance stages as a gate protective circuit for an MOS FET. However, there is no language therein with regard to technology for using a protective circuit with a thyristor structure with respect to a CDM mode static discharge in a fine-featured semiconductor device.
Additionally, in the Japanese Unexamined Patent Application S62-165966, there is indicat
Meier Stephen D.
NEC Corporation
Young & Thompson
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