Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2000-12-22
2002-05-07
Nelms, David (Department: 2818)
Static information storage and retrieval
Read only systems
Semiconductive
C365S230060, C365S130000
Reexamination Certificate
active
06385074
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits having memory cell arrays, and particularly to three-dimensional arrays incorporating multiple levels of memory cells.
2. Description of the Related Art
Semiconductor memories often use two different voltages to perform the read and write operations. In some memory technologies, particularly nonvolatile memories (i.e., memories having data stored which is not lost or altered when power is removed), the write voltage is often higher than the read voltage, with sufficient margin between the two voltages to ensure that memory cells are not written unintentionally when subjected to the read voltage.
Flash memories create a non-volatile state by accelerating electrons across a tunneling dielectric and storing the charge on a floating gate above a field effect transistor. On many earlier-developed devices, this acceleration of charge across the tunneling dielectric frequently required a voltage on the order of 12 volts. The remainder of the operations of the memory circuitry frequently required a voltage on the order of 5 volts, including reading the memory cells. Some commercially available devices required two different power supply voltages be supplied to operate the device. For example, a first power supply voltage equal to +5 volts (relative to “ground” or VSS) was typically utilized to power the normal read operation circuits, and was frequently called VDD. A second power supply voltage equal to +12 volts (also relative to VSS) was typically utilized to provide the write voltage for writing to the memory cells, and was frequently called VPP. Other commercially available devices require a single power supply voltage (e.g., VDD) to power the normal read operation, but include circuits to internally generate a write voltage, greater in magnitude than VDD, without requiring a separate power supply voltage be supplied by a user of the device.
As lower-voltage technologies have been developed, the magnitudes of the read voltage and the write voltage have both decreased. Read voltages of the order of 2.5-3.3 volts, and write voltages of the order of 8 volts, are more frequently encountered in more recently developed devices.
Other types of memory devices, including some volatile memories (i.e., having data stored which is typically lost when power is removed) utilize a write voltage which is different from its read voltage. For example, some static random access memory devices (SRAMs) provide a write voltage above VDD for writing to selected memory cells. Such devices are typically arranged to drive a selected word line during a write cycle to the write voltage which is above VDD, yet drive a selected word line during a read cycle to a lesser read voltage, such as VDD, or a voltage even lower than VDD.
While on-chip voltage generator circuits may relieve a user from supplying a second power supply voltage, such circuits frequently require a significant amount of layout area to implement, which may increase die size substantially, and consequently increase costs. Moreover, such voltage generator circuits also may consume a significant amount of power relative to the remainder of the circuit, and thus increase the current that must be supplied by the user (e.g., by the VDD power supply). Any increase in power dissipation may also increase the temperature of the die during operation. In a battery-powered environment, any increase in power consumed by a memory device may have significant implications for battery life, and any additional heat generated may also be difficult to dissipate. Consequently, continued improvements are desired, particularly as memory technology achieves continued advancements in bit density.
SUMMARY OF THE INVENTION
In an integrated circuit incorporating a three-dimensional memory array, vastly higher bit densities may be achieved compared to other types of memory arrays. Traditional implementations of on-chip voltage generators, such as charge pumps, may consume an undesirably large amount of die area, particularly relative to a higher bit density memory array. In one embodiment of the present invention incorporating a three-dimensional memory array formed entirely in layers above a semiconductor substrate, the area required to implement an on-chip voltage generator is reduced by laying out at least some of the voltage generator directly beneath the memory array.
In one preferred embodiment of the present invention, an integrated circuit device includes a three-dimensional memory array formed entirely in layers above a semiconductor substrate, and further includes array terminal circuitry for providing to one or more selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator. At least a portion of the write voltage generator is preferably implemented beneath the memory array, thus locating the write voltage generator near the selected memory cells without negatively impacting stacking of adjacent memory sub-arrays.
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U.S. Pat. application No. 09/748,815, files
Cleeves James M.
Farmwald Paul Michael
Johnson Mark G.
Lee Thomas H.
Subramanian Vivek
Le Thong
Matrix Semiconductor Inc.
Nelms David
Zagorin O'Brien & Graham LLP
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