Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-10-12
2002-05-07
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S065000, C365S185050, C365S117000, C365S185140
Reexamination Certificate
active
06385076
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory and its driving method, particularly relates to a nonvolatile memory that enables allowing a reading margin a sufficient value, in which disturbance in writing to a close cell is prevented and that is almost free of a malfunction.
2. Description of the Related Art
For a memory cell where each memory transistor having MFMIS structure which is an example of a semiconductor memory wherein data can be electrically written and data can be stored in a state of no power supply is arrayed in a matrix, 1T/2C memory cell structure composed by one selected transistor and two memory capacitors as shown in
FIG. 10
for example is proposed. In this structure, each one electrode of the memory capacitors is connected, is connected to the gate electrode of the selected transistor and each other electrode of the memory capacitors is connected to the source and the drain of the selected transistor. Therefore, there is a problem that source/drain voltage V
SD
and gate voltage V
G
cannot be independently set.
In this semiconductor memory, the source of each memory cell on each line in a transverse direction is connected to be a bit line BL
1
, BL
2
, - - - and the drain of each memory cell arranged in each column in a longitudinal direction is connected to be a word line WL
1
, WL
2
, - - - .
For this memory cell structure, FET having MFMIS structure wherein a metallic layer (M) and an insulator layer (I) intervene between ferroelectrics and semiconductor as a buffer layer as shown in a sectional explanatory drawing in
FIG. 11
is proposed. The FET having MFMIS structure is composed by sequentially laminating a gate oxide film
3
, a floating-gate
4
, a ferroelectric film
5
and a control gate
6
on a channel area formed between source area S and a drain area D of a semiconductor substrate
1
.
In this structure, normally, when the semiconductor substrate
1
is installed and positive voltage is applied to the control gate
6
as shown in
FIG. 12A
, polarization occurs in the ferroelectric film
5
. Even if the voltage applied to the control gate
6
is removed, negative charge is generated in a channel formation area by remanent polarization of the ferroelectric film
5
. This shall be a state of 1.
Conversely, when negative voltage is applied to the control gate
6
, polarization in a reverse direction occurs in the ferroelectric film
5
. Even if the voltage applied to the control gate
6
is removed, positive charge is generated in the channel formation area by remanent polarization of the ferroelectric film
5
. This shall be a state of 0. As described above, information ‘1’ or ‘0’ can be written to FET. FIGS.
12
A and
12
B respectively show a state in which information ‘1’ and ‘0’ is written.
Written information is read by applying reading voltage V
r
to the control gate. The reading voltage V
r
is set to a value between threshold voltage V
th1
in a state of 1 and threshold voltage V
th0
in a state of 0. It can be discriminated whether written information is 1 or 0 by detecting whether drain current flows or not when reading voltage V
r
is applied to the control gate
6
.
As described above, according to FET having MFMIS structure, one memory cell can be composed of one device and non-destructive reading can be satisfactorily performed.
Therefore, both can be identified.
However, in case the capacity C
f1
and C
f2
of memory capacitors are sufficiently larger than the capacity C
OX
depending upon a gate insulating film, gate voltage V
G
normally becomes a half of V
SD
, relationship between drain current I
D
and source/drain voltage V
SD
in writing ‘1’ and in writing ‘0’ are respectively as shown in
FIGS. 12A and 12B
and in reading, intermediate voltage is required to be set so that these values can be identified. Therefore, as shown in
FIG. 13
, in case reading voltage V
r
is set to a value between the minimum level in writing ‘1’ and the maximum level in writing ‘0’, there is a problem that a reading margin between 1 and 0 is small. Therefore, in the case of a cell to which ‘0’ is written, a coercive electric field may be also exceeded, it is judged that ‘1’ is written to a cell to which ‘0’ should be written and the reverse case occurs.
A nonvolatile memory wherein reliable reading characteristics can be acquired by allowing a reading margin a large value without causing wrong reading is desired.
There is a memory in which memory transistors having such MFMIS structure are arrayed in a matrix. Above all, a memory which is an example of a semiconductor memory in which data can be electrically written and which can store data in a state of no power supply wherein memory transistors having MFMIS structure are arrayed in a matrix is composed by composing one memory cell by one memory transistor and arraying memory cells lengthwise and crosswise as shown in
FIG. 14
for example. In this semiconductor memory, the source of each memory cell on each line in a transverse direction is connected to be a source line SL
1
, SL
2
, - - - , the drain of each memory cell arranged in each column in a longitudinal direction is connected to be a drain line DL
1
, DL
2
, - - - , substrate potential is connected to be a back gate line BL
1
, BL
2
, - - - and the control gate of each memory cell arranged on each line in the transverse direction is connected to be a word line WL
1
, WL
2
, - - - , WLn.
As for the structure of the memory cell, as shown in sectional explanatory drawings in
FIGS. 15A and 15B
, FET having MFMIS structure in which a metallic layer (M) and an insulator layer (I) intervene between ferroelectrics and semiconductor as a buffer layer is proposed. The FET having MFMIS structure is composed by sequentially laminating a gate oxide film
105
, a floating-gate
106
, a ferroelectric film
107
and a control gate
108
on a channel area
104
formed between a source area
102
and a drain area
103
on a semiconductor substrate
101
.
In this structure, normally, when the semiconductor substrate
101
is installed and positive voltage is applied to the control gate
108
as shown in
FIG. 15A
, polarization occurs in the ferroelectric film
107
. Even if the voltage applied to the control gate
108
is removed, negative charge is generated in a channel formation area CH by remanent polarization of the ferroelectric film
107
.
This shall be a state of 1.
Conversely, when negative voltage is applied to the control gate
108
, polarization occurs in the reverse direction in the ferroelectric film
108
. Even if the voltage applied to the control gate
108
is removed, positive charge is generated in the channel formation area CH by remanent polarization of the ferroelectric film
108
. This shall be a state of 0.
As described above, information ‘1’ or ‘0’ can be written to FET.
Reading written information is executed by applying reading voltage V
r
to the control gate. The reading voltage V
r
is set to a value between threshold voltage V
th1
in a state of 1 and threshold voltage V
th0
in a state of 0. It can be discriminated by detecting whether drain current flows or not when the reading voltage V
r
is applied to the control gate
108
whether written information is 1 or 0.
As described above, according to the FET having MFMIS structure, one memory cell can be composed by one device and non-destructive reading can be satisfactorily performed.
However, when a selected cell is set to a writing state as described above in writing data to the selected cell, an adjacent cell on the same line shares the source line SL and the word line WL of the corresponding cell and an adjacent cell in the same column shares the back gate line BL and the drain line DL. Therefore, also in an unselected cell, V
F
=V
C
to ⅓ of V
C
, a coercive electric field may be exceeded, writing is executed to a cell to be not written and the reverse case occurs.
Then, the provision of a nonvolatile memory wherein reliable writing characteristics can be acquired without causing
Morgan & Lewis & Bockius, LLP
Nguyen Viet Q.
Rohm & Co., Ltd.
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