Semiconductor interconnect barrier and manufacturing method...

Details Semiconductor interconnect barrier and manufacturing method... Semiconductor interconnect barrier and manufacturing method...

1999-01-13

2002-04-30

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S752000, C257S760000, C257S530000, C438S624000, C438S633000

Reexamination Certificate

active

06380625

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically interconnect barrier materials.
BACKGROUND ART
While manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique, starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein). A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent deposition of conductive material. A conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN) are used as channel barrier materials for copper.
According to conventional practices, a plurality of conductive layers are formed over a semiconductor substrate, and the uppermost conductive layer joined to a bonding pad for forming an external electrical connection. The upper conductive layers are typically reserved for power supply lines. The upper conductive layers carry a lot of current and dissipate a substantial amount of the power consumed by the integrated circuit. Therefore, it will be beneficial to use a metalization material with a lower resistance, such as copper, for the upper conductive layers. Accordingly, during the transition from aluminum to copper, it is quite common for an integrated circuit to have one or more of the upper conductive layers formed using copper as the metalization material, while the remaining lower conductive layers are formed using aluminum as the metalization material. The connection of a copper layer with an aluminum layer presents a dissimilar metal potential for electro-migration or interdiffusion. Thus, a suitable barrier layer is needed between the copper layer and the aluminum layer.
However, even with the various types of barrier layers, copper is still subject to strong electro-migration, or movement of copper atoms under current, which can lead to voids in the copper channels and vias. Copper also has poor surface adhesion. A solution, which would form an improved barrier layer between copper and various materials, including dielectrics and aluminum, and with better surface adhesion to reduce electro-migration, has been long sought. As the semiconductor industry is moving from aluminum to copper and other type of materials in order to obtain higher semiconductor circuit speeds, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a semiconductor interconnect barrier between channels and vias, and a manufacturing method therefor. The barrier material provides a better barrier between metal layers and an improved surface adhesion for the metal layers.
The present invention further provides a semiconductor interconnect barrier between channels and vias selected from tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof, formed atop a titanium nitride layer.
The present invention further provides a method of manufacturing semiconductor interconnect barriers between channels and vias of any desired material.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


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Kyung-Hoon Min et al. “Comparative study of tantalum and tantalum nitrides (Ta2N and TaN) as a diffusion barrier for Cu metallization”, J. Vac. Sci. Technol. B 14(5) pp. 3263-

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