Method of fabricating local interconnect

Details Method of fabricating local interconnect Method of fabricating local interconnect

1998-12-08

2002-05-21

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S599000, C438S598000, C438S597000

Reexamination Certificate

active

06391760

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating integrated circuit (ICs), and more particularly to a method of fabricating a local interconnect.
2. Description of the Related Art
For a metallization structure in a semiconductor, a barrier layer is usually formed between a metal layer and a silicon layer or a dielectric layer in order to avoid a phenomenon in which the metal layer diffuses into the silicon layer or the dielectric layer. This can also avoid the occurrence of shorts or openings in the metal layer, which result from the phenomena of spiking or electromigration.
FIG. 1
is a schematic cross-sectional view showing a conventional via structure comprising a barrier layer. A conductive layer
11
is formed on a semiconductor substrate
10
. A dielectric layer
12
with a via opening therein is formed on the conductive layer
11
. A conductive material
14
with good conductivity fills the via opening. Furthermore, a barrier layer
13
is formed between the conductive material
14
and the dielectric layer
12
or between the conductive material
14
and the conductive layer
11
to enhance the adhesion of the conductive material
14
and to prevent diffusion of the conductive material
14
.
FIG. 2
is a cross-sectional view showing a conventional dual damascene process. A conductive layer
21
is formed on a provided substrate
20
. A dielectric layer
22
is formed on the conductive layer
21
. A first opening
23
is formed in the dielectric layer
22
. A second opening
24
is formed in the dielectric layer
22
positioned under the first opening
23
to expose a part of the conductive layer
21
. A conformal barrier layer
25
is formed on the dielectric layer
22
. A conductive material
26
is formed on the barrier layer
25
to fill the first opening
23
and the second opening
24
. A conventional dual damascene process is thus completed.
In the design of a sub-micron integrated circuit, a local interconnect is formed to improve packing density. In circuit layout design, a local interconnect is used for horizontal connection between closely spaced devices.
Various types of local interconnects have been developed and applied in integrated circuit design. The material used for fabricating a local interconnect includes refractory metal silicide on poly-silicon, single or double doped poly-silicon, multi-layered refractory metal which is partially converted into silicide, or refractory metal formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
A via structure comprising a barrier layer described above is often required before performing a local interconnect process for horizontal connection between closely spaced devices. That means a barrier layer and a conductive layer overflowing a via opening or a trench have to be removed before performing the local interconnect process. Extra steps are thus required that not only complicate a device fabrication but also increase fabricating cost.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating a local interconnect using a barrier layer as a local interconnect without extra steps. A barrier layer as the local interconnect is very thick so that the filling ability of the barrier layer is good for small trenches or via openings. No other conductive material is formed after forming the barrier layer. A problem of difficulty in filling a conductive layer into a via opening or a trench after forming the barrier layer as seen in formation of a conventional local interconnect is thus avoided.
The invention achieves the above identified objects by providing a method of forming a local interconnect. A semiconductor is provided. An isolation structure, a transistor and a conductive layer are formed on the substrate. A dielectric layer with an opening is formed over the substrate. A part of the dielectric layer is removed by a photolithography and etching process to form a via opening to expose a part of the gate of the transistor or a part of the conductive layer. A conformal barrier layer is formed in the via opening and overflows the dielectric layer. A conductive plug is formed in the via opening. The barrier layer is patterned to form a local interconnect.


REFERENCES:
patent: 5188979 (1993-02-01), Filipiak
patent: 5488013 (1996-01-01), Geffken et al.
patent: 5936306 (1999-08-01), Jeng
patent: 5940735 (1999-08-01), Mehta et al.
patent: 5960303 (1999-09-01), Hill
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6004876 (1999-12-01), Kwon et al.
Jeng et al., “A Noevl TiSi2/TiN Clad Local Interconnect Technology”, May 1993, 1993 Symposium on VLSI Technology, pp. 105-106.*
D. Bartelink et al., “Interconnects for Submicron ASIC's”, May 1989, 1989 International Symposium on VLSI Technology, pp. 59-62.

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