Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1998-12-16
2002-07-02
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S230030, C365S230060
Reexamination Certificate
active
06414888
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device and, more specifically, to a semiconductor storage device (hereinafter referred to as a memory) having a line-to-line burn-in function of main word lines, applying a stress voltage between the main word lines in a burn-in state.
2. Description of Related Art
Techniques relating to a wafer stage burn-in operation on a layered memory having main word lines and sub-word lines (also called a double word line structure or divisional word line structure memory) are disclosed in, for instance, Japanese Patent Application Laid-Open Nos. 9-63273, 8-55497, and 9-17199. However, these publications are directed to a case of applying a burn-in stress voltage to sub-word lines en bloc, and do not disclose any technique of applying a stress voltage between main word lines.
The wiring pitch of layered word lines is increasingly decreased as the integration density increases. For example, at present, the line-to-line pitch of main word lines of DRAMs is smaller than 1 &mgr;m and even latent insulation defects are no longer negligible. Therefore, it is now strongly desired to provide a memory that can be subjected to a line-to-line burn-in operation for main word lines, particularly a wafer burn-in operation (hereinafter abbreviated as WBI).
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems in the art, and a first object of the invention is therefore to provide a semiconductor storage device in which WBI high-voltage stress can be applied between main word lines.
A second object of the invention is to provide a semiconductor storage device which enables chip size reduction by avoiding use of electrode pads dedicated to WBI that occupy a relatively large area and which allows WBI to be performed even in a resin-sealed package state.
A third object of the invention is to provide a semiconductor storage device which enables a long-pulse, long-cycle WBI operation, because a defect of insulation between main word lines has a very high insulation resistance value and hence in many cases a WBI operation using a short-pulse voltage cannot provide sufficiently high WBI effect.
According to a first aspect of the present invention, there is provided a semiconductor storage device comprising a cell array having a plurality of memory cells that are arranged in matrix form; a plurality of sub-word lines to serve as signal lines for selection in each row of the cell array; a plurality of main word lines to serve as signal lines for collective selection of a plurality of rows of the cell array via plural ones of the sub-word lines; a row decoder for generating a row selection signal for the main word lines and a row selection signal for the sub-word lines by decoding an address signal that is input externally; mutual switching means for switching among operation modes that includes an ordinary operation mode, a waiting mode, and a burn-in mode; and line-to-line burn-in means of the main word lines for applying a burn-in stress voltage between the main word lines in the burn-in mode.
In the semiconductor storage device, the semiconductor storage device may be of a wafer-like one, and the line-to-line burn-in means may apply a wafer burn-in stress voltage that is responsive to a stress application start signal between adjacent ones of the main word lines in a wafer burn-in state.
Here, the semiconductor storage device may be of a wafer-like one, the semiconductor storage device may further comprise an electrode pad to which a stress voltage is input externally; wiring means for supplying the stress voltage to every other one of the main word lines; stress application start signal generating means for generating a stress application start signal when the stress voltage is applied to the electrode pad; and control means of a line-to-line voltage between the main word lines for supplying the stress voltage to every other one of the main word lines in response to the stress application start signal after separating the row decoder from the main word lines.
Here, the semiconductor storage device may be of a wafer-like one, the semiconductor storage device may further comprise an electrode pad to which a stress voltage is input externally; wiring means for supplying the stress voltage from the electrode pad to every other one of the main word lines; wafer burn-in mode judgment circuit means for generating a stress application start signal in response to a wafer burn-in mode signal and an address signal that are input externally; and control means of a line-to-line voltage between the main word lines for supplying the stress voltage to every other one of the main word lines in response to the stress application start signal after separating the row decoder from the main word lines.
Here, the semiconductor storage device may be of a wafer-like one, the semiconductor storage device may further comprise wafer burn-in mode judgment circuit means for generating a stress application start signal in response to a wafer burn-in mode signal and an address signal that are input externally, and for generating a stress voltage for every other one of the main word lines; wiring means for supplying the stress voltage that has been generated by the wafer burn-in mode judgment circuit means to every other one of the main word lines; and control means of a line-to-line voltage between the main word lines for supplying the stress voltage to every other one of the main word lines in response to the stress application start signal after separating the row decoder from the main word lines.
Here, the semiconductor storage device may be of a wafer-like one, the semiconductor storage device may further comprise wafer burn-in mode judgment circuit means for generating a stress application start signal in response to a wafer burn-in mode signal and an address signal that are input externally, and for generating a stress voltage for every other one of the main word lines; and control means of a line-to-line voltage between main word lines for supplying the stress voltage to every other one of the main word lines via the row decoder in response to the stress application start signal, the stress voltage being generated for every other one of the main word lines.
In the semiconductor storage device, the semiconductor storage device may be accommodated in a package, and the line-to-line burn-in means of the main word lines may apply a package burn-in stress voltage that is responsive to a burn-in start signal in a package burn-in state between adjacent ones of the main word lines.
In the semiconductor storage device, the semiconductor storage device may be a dynamic random access memory in which a plurality of the main word lines and a plurality of the sub-word lines are formed so as to have a layered word line structure.
In the semiconductor storage device, the burn-in stress voltage may have repetitive voltage pulses having a pulse width that is longer than a clock pulse width of an external row address strobe control signal in the ordinary operation mode.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5276647 (1994-01-01), Matsui et al.
patent: 5986917 (1999-11-01), Lee
patent: 6026038 (2000-02-01), Cho et al.
patent: 6115319 (2000-09-01), Kinoshita et al.
“Wafer Burn-in (WBI) Technology for High Density DRAM”, Hiroyuki Noji, et al., Technical Reprot of IEICE, SDM94-22, ICD94-33 (1994-05) pp. 41-46.
Hoshita Tetsushi
Kitade Osamu
Ho Hoai V.
McDermott & Will & Emery
Nelms David
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