Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-08-30
2002-01-08
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S205000, C365S185330
Reexamination Certificate
active
06337808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory devices and, in particular, to flash memory devices having long endurance.
2. Description of the Related Art
Non-volatile memory, such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory) and Flash memory, is commonly used for storing data within computer systems. Non-volatile memory cells contain electrically isolated gates commonly referred to as floating gates. Data is stored in the memory cell by placing a charge on a cell's floating gate. The charge is used to indicate the binary state of the cell, either zero or one, which is typically indicated by a high threshold voltage or a low threshold voltage, respectively. The charge on a floating gate may be increased or removed through operations called program and erase.
Flash memory is desirable for certain applications as it does not need a constant power supply to retain its data and offers fast access times, low power consumption, and relative immunity to severe shock or vibration. These qualities, in combination with compact size, has propelled flash memory into a variety of uses in portable devices such as scanners, digital cameras, cell phones, pagers, and printers. Flash memory is similar to EPROM and EEPROM with the primary exceptions that flash memory must be erased in blocks rather than single bytes. In addition the blocks can be electrically erased, whereas an EPROM must be exposed to ultra-violet light to erase.
A typical flash memory cell
700
is shown in FIG.
7
. Memory cell
700
includes transistor
702
with floating gate
704
and control gate
706
. The floating gate
704
is electrically isolated in an insulative material, such as a gate oxide. Floating gate
704
may be a solid conductive material or may be constructed of a number of crystals of conductive material. Transistor
702
also includes source
708
and drain
710
. Source
708
is coupled to ground potential
712
and drain
710
is coupled to bit line
714
. Control gate
706
is coupled to word line
716
.
Transistor
702
is programmed by grounding its source
708
, applying a voltage to its control gate
706
, and connecting its drain
710
to a programming voltage V
DD
that is high relative to the operating voltage Vcc. A typical value for V
DD
is 10 volts, while a typical value for Vcc is 5 volts. Once transistor
702
is biased by the application of V
DD
, electrons tunnel through the insulative material to the floating gate
704
, producing a net negative charge on the floating gate
704
. This net negative charge shifts the threshold voltage (Vt) of the transistor
702
in the positive direction to a voltage that is greater than the normal operating voltage applied to the control gate
706
.
Transistor
702
is erased by grounding control gate
706
and applying a relatively high voltage (e.g., 12 volts) to the source
708
. This bias allows electrons to tunnel away from the floating gate
704
through the insulative material to be carried away by the large positive voltage on source
708
. The loss of electrons on the floating gate
704
shifts the threshold voltage Vt of the transistor
702
in the negative direction to a voltage that is less than the normal operating voltage applied to the control gate
706
.
After flash memory cell
700
is programmed or erased, the state of the storage transistor may then be “read” by determining whether the storage transistor conducts when the transistor is accessed. If the transistor
702
is programmed, i.e., there is a net negative charge on floating gate
704
, transistor
702
will not conduct when accessed since the threshold voltage Vt is a voltage greater than the normal operating voltage applied to the control gate. If, on the other hand, the transistor
702
is erased, i.e., there is no charge on floating gate
704
, transistor
704
will conduct when accessed since the threshold voltage Vt is less than the normal operating voltage applied to the control gate
706
.
A sense amplifier coupled across the source
708
and bit line
714
of flash memory cell
700
may be used to determine whether transistor
702
conducts based upon the current that flows out of cell
700
. A signal corresponding to the state of the cell
700
, i.e., either a logic high or a logic low, is output by the sense amplifier.
However, there are significant problems with conventional flash memory cells as described above. On such problem is that flash memories have a limited endurance, the number of erase and/or program cycles over which the cell remains operative and reliable. This limitation precludes the use of flash memories in applications requiring longevity, e.g. disk drive replacement. Current flash memories have an endurance of 10
5
to 10
7
cycles as compared to 10
9
cycles for a typical disk drive.
The basic physical phenomena or mechanism limiting the endurance of flash memories is fatigue or “wear-out” of the floating gate oxide. The total charge which can pass through a thin floating gate oxide is a measure of the endurance and is typically of the order of 10-15 coulombs/cm
2
. For example, current flash memories typically use a floating gate oxide having a thickness of approximately 100 Angstroms which, when charged by the accumulation of electrons during a program operation, results in about a 3 V change in V
t
. The capacitance of a 100 A gate oxide is about 3.2×10
−7
farads/cm
2
. Therefore, to achieve a 3 V change in V
t
a charge of 1×10
−6
coulombs/cm
2
is required. If the typical endurance of the gate oxide is 10 coulombs/cm
2
, the gate will allow 10
7
operational cycles before becoming unreliable. As noted above, a memory device capable of being used for 10
7
cycles is insufficient as replacement for most disk drive applications.
Thus there exists the need for a flash memory cell that provides reliable data storage while having an endurance of greater than 10
7
cycles.
SUMMARY OF THE INVENTION
The present invention provides a flash memory circuit having enhanced endurance properties. In a preferred embodiment, a differential flash memory cell and differential correlated double sampling sense amplifier are provided wherein a reduced charge differential on the floating gates of the memory cell is made possible and detectable by using a highly sensitive sense amplifier. A differential flash memory cell operating in the sub-threshold region is connected to a differential correlated double sampling sense amplifier to allow for charge differentials of less than 1.5×10
−8
coulombs/cm
2
between the two floating gates of each memory cell. This reduction in required charge greatly increases the long-term reliability and endurance of the memory cell, resulting in flash memory circuits which are capable of being used for over 10
9
cycles.
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Forbes; “Flash Memory With Long Endurance”; 8 total pages.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Nguyen Tuan T.
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