Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-04
2002-05-07
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000, C257S322000, C257S323000, C257S382000, C257S383000, C438S201000, C438S211000, C438S257000, C438S260000, C438S262000, C438S264000, C438S266000
Reexamination Certificate
active
06384450
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor memory device and a method of manufacturing the semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device in which resistance of source or drain diffusion layer can be effectively reduced and size of each memory cell can be reduced, and a method of manufacturing such memory device wherein number of process steps can be decreased to simplify manufacturing process of the memory device.
BACKGROUND OF THE INVENTION
In order to reduce resistance of a diffusion layer of a bit line or a source line of a semiconductor memory device, such as a flash memory device, there is known a method in which a metal layer is formed on the diffusion layer. Especially, with respect to the flash memory device having conductors or wirings each composed of a buried diffusion layer, three methods are considered to form the metal layer on the conductors. In the first method, a metal layer or a metal compound layer is formed on whole surface of a substrate, and thereafter unnecessary portions of the metal layer or the metal compound layer are removed by using a photolithography process and an etching process. In the second method, by using a salicidation (self-aligned silicidation), a titanium layer contacting a silicon layer or substrate is silicided to form titanium silicide layer. In the third method, a tungsten layer, for example, is grown as the metal layer, by using selective CVD.
However, when the salicidation of titanium is used as in the second method, there is a problem that titanium coagulates or coheres in the titanium silicide layer when oxidation is performed thereafter. Also, in the third method, when selective growth of tungsten is used, it is necessary to form a barrier metal layer between the conductors composed of the buried diffusion layer and the tungsten layer and to process the barrier metal layer by using process steps similar to those used in the first method. Therefore, conventionally, the first method had to be used to form the metal layer on the buried diffusion layer.
FIGS. 5A and 5B
illustrates a structure of a flash memory device fabricated by using a prior art method, that is, the first method mentioned above.
FIG. 5A
is a plan view of the flash memory device, and
FIG. 5B
is a cross sectional view taken along the line A—A of FIG.
5
A.
As shown in
FIG. 5A
, a plurality of control gate conductors
39
which also constitute word lines are disposed in a lateral direction in the drawing. Under the control gate conductors
39
, a source region
30
and a drain region
31
each made of a buried diffusion layer are formed in a vertical direction via an interlayer oxide film
37
and so on. The drain region
31
also functions as a bit line.
As shown in
FIG. 5B
, on a channel region between the source region
30
and the drain region
31
, a tunnel oxide film
34
, a floating gate
35
, an ONO film (oxide film-nitride film-oxide film)
38
, and the control gate
39
are formed sequentially from the bottom. In order to reduce the resistance of each of the conductors of the buried diffusion layer, a titanium nitride layer
36
is formed as a metal layer or a metallic compound layer on the surface of each of the source region
30
and the drain region
31
. On the side surfaces of the floating gate
35
, oxide film sidewall spacers
33
are formed and isolate the floating gate
35
and the titanium nitride layer
36
from each other. The titanium nitride layer
36
also extends from the surface of each of the source region
30
and the drain region
31
along the side surface of the sidewall spacers
33
.
With reference to
FIGS. 6A through 6D
, explanation will be made on a method of manufacturing the conventional flash memory device shown in
FIGS. 5A and 5B
.
First, as shown in
FIG. 6A
, a semiconductor substrate
29
in which element isolation regions
32
having a structure such as STI (Shallow Trench Isolation) and a tunnel oxide film
34
are formed is prepared. On the semiconductor substrate
29
, a polycrystalline silicon (polysilicon) layer is formed by using, for example, CVD (Chemical Vapor Deposition). The polysilicon layer is patterned by using a photolithography process such that a floating gate
35
made of polysilicon is disposed in the direction of the bit line. Further, a silicon oxide film is formed on whole surface of the semiconductor substrate and the silicon oxide film is etched back by anisotropic etching, so that oxide film sidewall spacers
33
are formed on the side surface of the floating gate
35
. Thereafter, buried diffusion layers of the source
30
and the drain
31
are formed by ion implantation.
Then, as shown in
FIG. 6B
, high refractory metal or metal compound, for example, titanium nitride in this case, is sputtered on whole surface of the semiconductor substrate to form a titanium nitride layer
40
.
Further, as shown in
FIG. 6C
, the titanium nitride layer
40
is patterned by using a photolithography process and an etching process such that portions of the titanium nitride layer
40
on the floating gate
35
and on the element isolation region
32
are removed. In this case, as shown in
FIG. 6C
, it is required that both ends of each of the remained titanium nitride layers
40
are on the oxide film sidewall spacer
33
and on the element isolating region
32
. If the titanium nitride layer
40
is patterned such that end portions of the remained titanium nitride layer
40
are on the diffusion layers
30
and
31
, the semiconductor substrate
29
including the diffusion layers
30
and
31
is exposed and over-etched by the etching process of patterning the titanium nitride layer
40
.
As shown in
FIG. 6D
, an oxide film is then grown on whole surface of the semiconductor substrate by using, for example, CVD, and this oxide film is etched back to form an interlayer oxide film
37
, such that the titanium nitride layers
40
are buried under the interlayer oxide film
37
. Thereafter, portion of the oxide film on the floating gate
35
is selectively removed by using a photolithography process and an etching process.
Then, the ONO film
38
and a tungstenpolyside layer for forming a control gate
39
are grown on whole surface of the substrate. Thereafter, patterning of the control gate
39
, the ONO film
38
and the floating gate
35
is performed by using a photolithography process and an etching process, and a semiconductor memory device having a configuration shown in
FIGS. 5A and 5B
is obtained.
The prior art technique described above has the following problems.
In the first problem, when a metal layer such as a titanium nitride layer
36
is formed, a photolithography process is required which adds to the number of process steps to fabricate a memory device. Since the metal layer is selectively formed on the buried diffusion layer, the photolithography process is required.
In the second problem, when a portion of the interlayer oxide film on each of the floating gates is removed, a photolithography process is required which adds to the number of process steps to fabricate a memory device. As shown in
FIG. 6C
, if each of the metal layer, such as the titanium nitride layer
40
, is formed by using a photolithography process and an etching process such that an end portion of the titanium nitride layer
40
comes near the upper end of the oxide film sidewall spacer
33
, the top tip portion of the titanium nitride layer
40
protrudes in a direction perpendicular to the substrate
29
from the surface of the portion near the upper end of the oxide film sidewall spacer
33
by the amount corresponding to the thickness of the titanium nitride layer
40
, so that the position of the top tip portion of the titanium nitride layer
40
becomes higher than the upper surface of the floating gate
35
. If, after forming the oxide film
37
on the floating gate
35
, the oxide film
37
is etched back until the floating gate
35
is exposed, a portion of the titanium nitride layer
40
is also expo
Hidaka Ken-Ichi
Tsukiji Masaru
Kang Donghee
Thomas Tom
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