Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1999-03-17
2002-05-14
Gossage, Glenn (Department: 2187)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S052000, C711S109000, C365S221000
Reexamination Certificate
active
06389489
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to data processing systems and more particularly to data buffering in a data processing system.
BACKGROUND OF THE INVENTION
Data or information in computers is processed in a predominantly serial fashion. Many times there are sources and destinations of data that are connected by buses. Usually there is a mismatch in the rate at which data is produced and the rate at which data can be accepted. One way to accommodate a mismatch in data rates is to use a first-in, first-out (FIFO) buffer between the data source and data destination.
Certain FIFOs contain threshold values that serve to control their operation. For instance, a threshold might be set to generate an interrupt to the data source if the source is about to exceed the capacity of the FIFO (overrun). Conversely, a threshold might be set to disable the output of data until an uninterrupted supply of data can be guaranteed (underrun). Some communications protocols specify fixed length transmissions of blocks, or packets, of data. If one or more gaps are interjected into the transmission because of, for example, an underrun or overrun, then one or more data beats at the end of the transmission may be ignored by the destination to ensure that an output data stream is transmitted without interruption and contains no bubbles or gaps.
REFERENCES:
patent: 4683534 (1987-07-01), Tietjen et al.
patent: 4954987 (1990-09-01), Auvinen et al.
patent: 5121346 (1992-06-01), McClure
patent: 5155810 (1992-10-01), McNamara, Jr.
patent: 5262997 (1993-11-01), Lee
patent: 5278956 (1994-01-01), Thomsen et al.
patent: 5287481 (1994-02-01), Lin
patent: 5295246 (1994-03-01), Bischoff et al.
patent: 5327545 (1994-07-01), Begun et al.
patent: 5602850 (1997-02-01), Wilkinson et al.
patent: 5732286 (1998-03-01), Leger
patent: 5771356 (1998-06-01), Leger et al.
patent: 5884099 (1999-03-01), Klingelhofer
patent: 6134629 (2000-10-01), L'Ecuyer
patent: 0 489 504 (1992-06-01), None
Rosenberg, “Dictionary of Computers, Information Processing & Telecommunications”, Second Edition, pp 9 and 470 (1984).
Agrawal Ritesh Radheshyam
Stone Chris Randall
Chastain Lee E.
Gossage Glenn
Hill Daniel D.
LandOfFree
Data processing system having a fifo buffer with variable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing system having a fifo buffer with variable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system having a fifo buffer with variable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2859982