Degenerate network for PLD and plane

Details Degenerate network for PLD and plane Degenerate network for PLD and plane

2000-05-08

2002-04-09

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S047000

Reexamination Certificate

active

06369609

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for an AND plane of a programmable logic device generally and, more particularly, to a method and/or architecture for a degenerate network for an AND plane of a programmable logic device.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a schematic diagram of a circuit
10
illustrating an implementation of an AND plane is shown. The circuit
10
illustrates a row of a 39-input AND plane. The circuit
10
provides for each of the 39 inputs (e.g., IT
0
-IT
38
) and a digital complement of each of 39 inputs (e.g., ITB
0
-ITB
38
) to be wire NORed. Seventy-eight configuration bits M control which of the inputs IT
0
-IT
38
and complements ITB
0
-ITB
38
are NORed. A sense amplifier
12
generates a row output in response to the wired NOR result.
Disadvantages of the sense amplifier
12
based AND plane include (i) sensitivity to the switching of a number of pull down paths, (ii) susceptibility to glitching, and (iii) continuous DC power consumption.
SUMMARY OF THE INVENTION
The present invention concerns a programmable logic device comprising one or more first stages and one or more second stages. The one or more first stages may comprise one or more gates of a first type each having a first number of inputs. The one or more second stages may comprise one or more gates of a second type each having a second number of inputs, wherein said first and second stages are interlaced.
The objects, features and advantages of the present invention include providing a method and/or architecture for a degenerate network for an AND plane of a programmable logic device that may (i) provide minimal skew, (ii) use symmetric gates, (iii) use a particular type of gate for each stage, (iv) connect un-used inputs to a voltage or ground supply, (v) provide minimal propagation delay, (vi) provide zero DC power consumption, (vii) provide glitch free operation and/or (v) provide a fully CMOS, degenerate N-input AND plane.


REFERENCES:
patent: 4159512 (1979-06-01), Geerling
patent: 4933736 (1990-06-01), Conner et al.
patent: 5028814 (1991-07-01), Sung et al.
patent: 5087837 (1992-02-01), Cline
patent: 5144582 (1992-09-01), Steele
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5714890 (1998-02-01), Cline
patent: 5789945 (1998-08-01), Cline
patent: 5889416 (1999-03-01), Lovett

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