Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-06-30
2002-07-16
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S154000, C711S170000
Reexamination Certificate
active
06421765
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory in processor-based or microcontroller-based systems, and more particularly, to an apparatus and method of selecting functional space in a low pin count memory device.
2. Description of the Related Art
In processor-based systems such as computers, an address space may correspond to several functional spaces. To allow the processor to access these functional spaces, extra signals or signal lines are used. For example, a dedicated pin is typically provided on a chip so as to access a separate functional space in a memory component, such as register space. Such a separate functional space in the memory component is typically mapped to the same address space as the main memory, i.e., to memory space. This mapping scheme presents several problems, the most significant of which is the resulting error created when an access to the main memory is mapped to that intended for the register space. The implementation of a dedicated pin for accessing one of several functional spaces is particularly problematic in Low Pin Count (LPC) (refer to http://developer.intel.com/design/chipsets/industry/lpc
—
100.pdf) memory devices, as a minimal number of pins are implemented in these devices so as to reduce the requirements for space, cost and testing procedures.
Accordingly, there is a need in the technology for an apparatus and method for overcoming the aforementioned problem. In particular, there is a need for an apparatus and method for allocating functional space in an LPC memory device so as to overcome the aforementioned problem.
BRIEF SUMMARY OF THE INVENTION
The present invention is an apparatus and method for selecting one of a first and a second storage element in response to a control signal issued by a processor in a low-pin count device. The apparatus comprises a decoder to receive the control signal and an address signal having a select bit indicative of one of the first and the second storage elements. The decoder generates a select signal to access one of the first and the second storage elements based on the select bit.
REFERENCES:
patent: 4797812 (1989-01-01), Kihara
patent: 5060192 (1991-10-01), Young et al.
patent: 5179534 (1993-01-01), Pierce et al.
patent: 5369752 (1994-11-01), Giles et al.
patent: 5390317 (1995-02-01), Weiss et al.
patent: 6263473 (2001-07-01), Kamada
Low Pin Count (LPC) Interface Specification, Revision 1.0, Sep. 29, 1997.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Thai Tuan V.
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