Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1998-10-10
2002-04-09
Ellis, Richard L. (Department: 2651)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S224000, C712S228000, C712S235000, C712S239000
Reexamination Certificate
active
06370639
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the architecture of a floating-point unit in a computer and, more particularly, to a floating-point unit which utilizes two or more status fields for enhanced performance.
BACKGROUND OF THE INVENTION
Floating-point units for performing floating arithmetic in a computer typically include a floating-point computation unit, a set of floating-point registers for holding operands, intermediate results and the like, and a floating-point status register. The floating-point computation unit is typically pipelined so that different operations of different floating-point calculations may be performed simultaneously. The floating-point status register includes control information, such as precision control and rounding control, that controls the floating-point calculation. In addition, the floating-point status register includes flag information, such as overflow and zero divide flags which record exceptions that occurred during a floating-point calculation.
Floating-point units are typically configured for compliance with ANSI/IEEE floating-point standard no. 754-1985. This standard specifies floating-point data types, various arithmetic and other operations, and handling of exceptions. It is desirable to provide a floating-point unit which meets the IEEE floating-point standard in all respects and which has additional features that overcome drawbacks in the prior art and thereby enhance performance.
The conventional floating-point status register is a hardware register that contains control information and flag information as described above. The control information is set by software, and the flag information is set in response to execution of a floating-point calculation. Conventionally, the control information is modified by copying the contents of the floating-point status register to a general purpose register, modifying the contents of the general purpose register and then writing the contents of the general purpose register back to the floating-point status register. The flag information in the floating-point status register may be cleared in a similar manner. Thus, the operations of updating control information and clearing flag information are relatively time-consuming. Furthermore, when the control information in the floating-point status register is updated, it is necessary to flush the pipelined floating-point computation unit, thereby aborting partially completed calculations and degrading performance. Because of these drawbacks, frequent updating of the floating-point status register is typically avoided.
The execution of speculative operations is a known technique for enhancing processor performance. In order to maximize utilization of a processor, instructions that appear later in a program may be scheduled for execution in parallel with earlier instructions, if the operands necessary for execution are available. Because branch instructions are usually present in the program, it may not be possible to determine in advance whether an instruction will require execution. However, if resources of the processor are otherwise idle, the performance of the processor may be improved by executing instructions speculatively, even though execution of those instructions may later be determined to be unnecessary. Execution of an instruction that follows a branch instruction before execution of the branch instruction is known as speculative execution. If the program ultimately requires execution of the instruction that was executed speculatively, an improvement in performance is obtained. If execution of the speculative instruction is not required, the result is discarded.
The floating-point status register contains flag information in the form of flag bits, or simply “flags”. The flags record exceptions that occur during execution of a floating-point calculation. Exceptions may also create interruptions. In the case of speculative execution, it is undesirable to report an exception immediately because the result of the speculative execution may later be discarded. Nonetheless, floating-point units typically handle flags for speculative operations in the same manner as nonspeculative operations.
One of the exceptions that is recorded in the flag information is an overflow exception, where the exponent in the result of the calculation is outside a specified range. The range may be established by the memory format used to store floating-point numbers or by the user of the result. However, the floating-point unit may have the capability of handling floating-point numbers which are outside the range that causes the reporting of an overflow exception. This may give rise to the reporting of overflow exceptions unnecessarily. For example, floating-point calculations typically involve several operations. In certain calculations, the result of an intermediate operation may produce an overflow exception, even though the final result would not produce an overflow exception if the calculation was s permitted to continue. It is desirable to avoid reporting exceptions unnecessarily, since execution may be delayed or terminated.
Another aspect of handling floating numbers during floating-point calculations relates to “big endian” and “little endian” formats. In big endian format, a data word is stored in memory with its most significant byte corresponding to the most significant byte of the memory word. In little endian format, a data word is stored in memory with its least significant byte corresponding to the most significant byte of the memory word. A processor may be required to handle both formats efficiently.
It is desirable to provide floating-point architectures which alleviate or eliminate one or more of the above-described drawbacks.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method is provided for operating a computer comprising a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register includes a main status field and at least one alternate status field. Each of the status fields contains flag information and control information. A first operation is performed in the floating-point computation unit, and the first operation is associated with the main status field in the floating-point status register. A second operation is performed in the floating-point computation unit, and the second operation is associated with the alternate status field in the floating-point status register. Thus, the first and second operations have independent flag and control information in the main and alternate status fields, respectively. The first and second operations may be associated with the main and alternate status fields, respectively, in response to control bits in floating-point instructions which specify the first and second operations.
The first operation may comprise a non-speculative operation, and the second operation may comprise a speculative operation. The flag information in the alternate status field which is associated with the speculative operation is checked when the speculative operation is committed. If the flag information in the alternate status field does not indicate an exception, execution of a third operation may proceed.
The flag information may be checked by comparing the flag information in the alternate status field with the flag information in the main status field and with trap enable bits in the floating-point status register. A branch to a recovery operation occurs when the flag information in the alternate status field is different from the flag information in the main status field, or when the flag information in the alternate status field corresponds to a trap which is enabled in the floating-point status register. The recovery operation may comprise reexecuting the speculative operation and associating reexecution of the speculative operation with the main status field in the floating-point status register.
More than one speculative operation may be associated with one alternate status field in the floating-point sta
Colon-Bonet Glenn T.
Doshi Gautam B.
Golliver Roger
Huck Jerome C.
Karp Alan H.
Ellis Richard L.
Institute for the Development of Emerging Architectures L.L.C.
Patel Gautam R.
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