Memory failure analysis device that records which regions...

Details Memory failure analysis device that records which regions... Memory failure analysis device that records which regions...

1999-06-28

2002-09-10

Verbrugge, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C714S723000

Reexamination Certificate

active

06449704

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for transferring data from a memory, and more particularly to a data transfer technique used for a memory device testing apparatus.
2. Description of Related Art
FIG. 1
shows a conventional configuration for transferring a fail signal stored in a failure analysis memory unit
10
to a memory failure remedy analysis unit
30
in a memory device testing apparatus to remedy a fail memory device.
The failure analysis memory unit
10
has a data storage memory
12
, an address generation control unit
14
, an address pointer
16
, a multiplexer
18
, and a data storage memory register
20
. The memory failure remedy analysis unit
30
has a fail buffer memory
34
and an address pointer
36
. When a defective cell is present in the memory device, a fail signal
91
which indicates the content of the failure is stored in an address in the data storage memory that corresponds to the address signal
65
of the defective cell of the test memory device. The address signal
65
passes through the input terminal on the 0-side of the multiplexer
18
and is input to the data storage memory
12
. The data storage memory
12
has the same memory capacity as the memory device being tested.
The address pointer
16
outputs an address signal incremented by a clock signal. The address signal generated by the address pointer
16
passes through the input terminal on the 1-side of the multiplexer
18
, and is input to the address pin of the data storage memory
12
. In this case, a read request signal is input to the control pin of the data storage memory
12
. As a result, the data containing the fail signal stored in the data storage memory
12
is read and transferred by the memory failure remedy analysis unit
30
.
The address pointer
36
o f the memory failure remedy analysis unit
30
receives substantially the same clock signal as the clock signal input to the address pointer
16
. The address pointer
36
generates an address signal that accesses the fail buffer memory
34
. This address signal is incremented by a click signal. The address signal generated by the address pointer
36
and the transfer data signal
22
output from the data storage memory
12
a re input in synchronization to the fail buffer memory
34
. A write request signal is input to the control pin of the fail buffer memory
34
. The transfer data signal
22
is written onto the address designated by the address signal input from the address pointer
36
to the fail buffer memory
34
. The data storage memory register
20
stores the value of the end address of the data storage memory
12
. The address generation control unit
14
compares the value incremented by the address pointer
36
with the value stored in the data storage memory register
20
. When the value incremented by the address pointer
36
agrees with the value stored in the data storage memory register
20
, all the data inside the data storage memory
12
is transferred. In this case, the transfer operation is completed. After this, the address pointers
16
and
36
are reset and returned to the initial states.
In t he conventional configuration shown in
FIG. 1
, regardless of the number of defective cells, all the data in the data storage memory
12
from the start address to the end address must be transferred. For example, when i t takes Tread (sec) to read the data stored in
1
address and the address of the test memory device has the length of 64M words, it takes 64M×Tread (sec) to transfer all the data stored in the data storage memory
12
. Hence, as the capacity of the test memory device such as a DRAM, SDRAM or the like is increased, the length of time required to transfer all the data from the failure analysis memory unit
10
to the memory failure remedy analysis unit
30
is increased accordingly.
SUMMARY OF THE INVENTION
In order to solve the above-stated problem, the present invention provides a data transfer apparatus which transfers data from a data storage memory that can be divided into at least two sub-address spaces. This data transfer apparatus has a compact memory for storing transfer data existence information which indicates whether transfer data to be transferred exists or not in each of the sub address spaces, a sub memory address designation unit for generating a sub address signal that designates the sub address space having the transfer data based on an output from the compact memory, and a read address control unit which reads and transfers the transfer data stored in the sub address space indicated by the sub address signal output from the sub memory address designation unit.
The pre sent invention also provides a memory device testing apparatus for testing a memory device. This memory device testing apparatus has a pattern generator which generates a control signal for controlling the memory device, an address signal for accessing said memory device, and a test data signal for representing test data to be written on the memory device, a memory device plug-in unit which enables test data to be written on the memory device and the test data to be read from the memory device by having the memory device plugged in and supplying the control signal and the address signal generated by the pattern generator to the memory device, a comparison device which compares expectation value data equal to the test data supplied to the memory device to be written on the memory device with the test data that has been read after being written on the memory device, and outputs a fail signal that indicates the content of a defect when the memory device has a defective spot, a failure analysis memory unit having a data storage memory that is divided into at least two sub address spaces including an address that corresponds to the address of the defective spot of the memory device onto which the fail signal output from the comparison device is written, and a compact memory which stores failure information that indicates existence of said defective spot in the sub address space, and a memory failure remedy analysis unit to which the fail signal written on the data storage memory is transferred. Based on the failure information stored in the compact memory, the fail signal written on the sub address space in which the defective spot exists is transferred to the memory failure remedy analysis unit.
Moreover, the present invention also provides a data transfer method for transferring data from a data storage memory divisible into at least two sub address spaces. This data transfer method has the first step of storing in a compact memory having a memory capacity smaller than a memory capacity of the data storage memory transfer data existence information which indicates whether transfer data to be transferred exists or not in each of said sub address spaces, the second step of generating a sub address signal for designating the sub address space in which the transfer data is stored based on the transfer data existence information stored in the compact memory, and the third step of reading and transferring the transfer data stored in the sub address space designated by the generated sub address signal.
Moreover, the present invention also provides a memory device testing method for testing a memory device using a data storage memory that is divided into at least two sub address spaces. This memory device testing method has the first step of having a pattern generator generate a control signal for controlling the memory device, an address signal for accessing the memory device, and a test data signal for representing test data to be written on the memory device, the second step of writing test data on the memory device by supplying the control signal and the address signal generated by the pattern generator to the memory device, the third step of comparing expectation value data identical to the test data supplied to the memory device to be written on the memory device with the test data that has been read after being written on the memory devi

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