Damascene structure and method of making

Details Damascene structure and method of making Damascene structure and method of making

2000-08-28

2002-09-17

Ho, Hoai V. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S638000

Reexamination Certificate

active

06451683

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods of making such devices. More particularly, the invention relates to a method of forming damascene structures.
BACKGROUND OF THE INVENTION
The integration of a large number of components on a single integrated circuit (IC) chip requires complex interconnects. Ideally, the interconnect structures should be fabricated with minimal signal delay and optimal packing density. The reliability and performance of integrated circuits may be affected by the qualities of their interconnect structures.
Advanced multiple metallization layers have been used to accommodate higher packing densities as devices shrink below sub-0.25 micron design rules. One such metallization scheme is a dual damascene structure formed by a dual damascene process. The dual damascene process is a two-step sequential mask/etch process to form a two-level structure, such as a via connected to a metal line situated above the via.
As illustrated in
FIG. 1
, a known dual damascene process begins with the deposition of a first insulating layer
14
over a first level interconnect metal layer
12
, which in turn is formed over or within a semiconductor substrate
10
. A second insulating layer
16
is next formed over the first insulating layer
14
. An etch stop layer
15
is typically formed between the first and second insulating layers
14
,
16
. The second insulating layer
16
is patterned by photolithography with a first mask (not shown) to form a trench
17
corresponding to a metal line of a second level interconnect. The etch stop layer
15
prevents the upper level trench pattern
17
from being etched through to the first insulating layer
14
.
As illustrated in
FIG. 2
, a second masking step followed by an etch step are applied to form a via
18
through the etch stop layer
15
and the first insulating layer
14
. After the etching is completed, both the trench
17
and the via
18
are filled with metal
20
, which is typically copper (Cu), to form a damascene structure
25
, as illustrated in FIG.
3
.
If desired, a second etch stop layer, such as stop layer
29
of
FIG. 4
, may be formed between the substrate
10
and the first insulating layer
14
during the formation of a dual damascene structure
26
. In any event, and in contrast to a single damascene process, the via and the trench are simultaneously filled with metal. Thus, compared to the single damascene process, the dual damascene process offers the advantage of process simplification and low manufacturing cost.
Dual damascene processes such as the ones described above pose significant problems. One of the problems is caused by the use of one or more etch stop layers. The etch stop layers
15
,
29
prevent the damascene patterns
17
,
18
from extending into or through the underlying layers
14
,
10
. Although the advantages of using the etch stop layers are significant, the process is complex since separate depositions are required for the etch stop layers.
In addition, the most commonly used etch stop material, silicon nitride (Si
3
N
4
), has a rather high dielectric constant (k) (approximately 7), which does not satisfy anymore the requirement of resistance-capacitance delay regarding the parasitic capacitance generated by an intermetal insulating layer. As integrated circuits become denser, it is increasingly important to minimize stray capacitance between the metal layers. This is accomplished by using intermetal insulating layers that have a low dielectric constant, such as, for example, organic dielectric materials. Silicon nitride does not satisfy the requirement of small stray capacitance of advanced damascene structures.
Accordingly, there is a need for an improved damascene process which reduces production costs and increases productivity. There is also a need for a damascene process that does not require etch stop layers, as well as a method for decreasing the stray capacitance between the metal layers of damascene structures.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a damascene interconnect structure in a semiconductor device. According to one aspect of the invention, productivity can be increased since fewer processing steps are required. According to another aspect of the invention, the use of high dielectric etch stop material may be avoided, so as to reduce or minimize stray capacitance.
In an exemplary embodiment, a plurality of low dielectric constant materials are selected with similar methods of formation, as well as with similar capacities to withstand physical and thermal stress. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed according to damascene processing. Since the low dielectric constant materials are selected so that the etchant available for each one has only a small etch rate relative to the other low dielectric constant materials, the plurality of low dielectric constant materials act as etch stops during the fabrication of damascene structures. This way, the etch stop layers employed in the prior art are eliminated and the number of fabrication steps is reduced.
Additional advantages of the present invention will be more apparent from the detailed description and accompanying drawings, which illustrate preferred embodiments of the invention.


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patent: 6060404 (2000-05-01), Ngo et al.
patent: 6063711 (2000-05-01), Chao et al.
patent: 6071805 (2000-06-01), Liu
patent: 6071809 (2000-06-01), Zhao
patent: 6187661 (2001-02-01), Lou
patent: 6242339 (2001-06-01), Aoi
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