Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-04-03
2002-09-10
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000
Reexamination Certificate
active
06448602
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to arrangement of memory blocks and peripheral circuits thereof in a semiconductor memory device.
2. Description of the Background Art
In these years, semiconductor memory devices, particularly DRAMs (Dynamic Random Access Memories), are highly integrated with even larger capacity. With such increase in capacity, a memory cell array is divided into a great number of memory blocks (subarrays) because bit lines and word lines are divided into multiple bit lines and word lines to cope with increase in power consumption and delay time and decrease in signal voltage in a memory cell. Generally, since a semiconductor memory device has storage capacity of 2
N
bits which is the Nth power of 2, memory blocks are arranged in an even number of rows and columns.
FIGS. 16 and 17
show layouts of conventional DRAMs. These figures are shown in, for example,
FIG. 1.14
in
VLSI Memory
by Kiyoo Ito, published by Baifukan Press, p. 19.
FIG. 16
shows an internal structure of a DRAM of 64 K bits. Referring to
FIG. 16
, the DRAM includes a semiconductor substrate
10
, memory cell arrays MA
1
and MA
2
formed on semiconductor substrate
101
a row decoder
42
arranged to cross vertically over memory cell array MA
1
or MA
2
, a column decoder
43
arranged to cross horizontally over memory cell array MA
1
or MA
2
, a peripheral circuit
11
for memory cell array MA
1
, and a peripheral circuit
12
for memory cell array MA
2
.
FIG. 17
shows an internal structure of a DRAM of 64 M bits. Referring to
FIG. 17
, this DRAM includes semiconductor substrate
10
, memory cell arrays MA
1
-MA
4
formed on semiconductor substrate
10
, row decoder
42
arranged to cross horizontally over memory cell array MA
1
-MA
4
, column decoder
43
arranged adjacent to one shorter side of each of memory cell arrays MA
1
-MA
4
, and a peripheral circuit
11
for memory cell arrays MA
1
-MA
4
.
Each of memory cell arrays MA
1
-MA
4
shown in
FIG. 17
is divided into 64 subarrays.
FIG. 17
shows only subarrays SA
1
-SA
64
in memory cell array MA
3
. Since this DRAM has storage capacity of 64 M bits, each of memory cell arrays MA
1
-MA
4
includes 16M (16×220) memory cells, and each of subarrays SA
1
-SA
64
includes 256 K (256×210) memory cells. Therefore, in this DRAM subarrays are arranged in 2 K rows and 128 columns.
Peripheral circuit
11
includes a control circuit (not shown) for controlling memory cell arrays MA
1
-MA
4
and an input/output interface circuit (not shown). The input/output interface circuit is a circuit for converting an externally applied control signal and the write data to an internal signal to be supplied to the control circuit or outputting to outside the readout data transferred from memory cell arrays MA
1
-MA
4
to the control circuit. The control circuit is a circuit for controlling memory cell arrays MA
1
-MA
4
based on the data or the control signal applied to the input/output interface circuit.
Since a DRAM includes 2
N
memory cells, which is the Nth power of 2, it has been common to arrange subarrays in even number of rows and even number of columns. However, with an increase in capacity, the number of subarrays tends to grow increasingly. As a result, it is difficult to implement a DRAM of 1 G bit by the arrangement methods shown in
FIGS. 16 and 17
. More specifically, a memory cell array must be divided into multiple subarrays in a DRAM of 1 G bit, leading to unequal distances from the peripheral circuit to respective subarrays and to unequal signal delays.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor memory device having a large storage capacity.
Another object of the present invention is to provide a semiconductor memory device with equal signal delay.
Still another object of the present invention is to provide a novel method of arranging a plurality of memory blocks and a peripheral circuit thereof.
According to one aspect of the present invention, a semiconductor memory device includes a semiconductor substrate, a plurality of memory blocks, and a peripheral circuit therefor. The plurality of memory blocks are arranged on the semiconductor substrate to surround the center thereof. Each memory block includes a plurality of word lines, a plurality of bit lines crossing the word lines and a plurality of memory cells each corresponding to a crossing point of the word line and the bit line. The peripheral circuit is arranged on the semiconductor substrate at the center thereof.
According to another aspect of the present invention, a semiconductor memory device includes eight memory blocks and a peripheral circuit therefor. The eight memory blocks are arranged in three rows and three columns except for the second row of the second column. Each memory block includes a plurality of word lines, a plurality of bit lines crossing the word lines and a plurality of memory cells each corresponding to a crossing point of the word line and the bit line. The peripheral circuit is disposed at the second row of the second column.
According to still another aspect of the present invention, a semiconductor memory device includes four unit blocks. Each unit block includes eight memory blocks and a peripheral circuit therefor. Four unit blocks are arranged in two rows and two columns. Eight memory blocks are arranged in three rows and three columns except for the second row of the second column. Each memory block includes a plurality of word lines, a plurality of bit lines crossing the word lines and a plurality of memory cells each corresponding to a crossing point of the word line and the bit line. The peripheral circuit is disposed at the second row of the second column.
Therefore, according to the present invention, the distance from the peripheral circuit to each memory block is substantially equal, resulting in substantially equal signal delay. Consequently, a semiconductor memory device with a large storage capacity can be easily implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4864381 (1989-09-01), Seefeldt et al.
patent: 5214657 (1993-05-01), Farnworth et al.
patent: 5222042 (1993-06-01), Ichiguchi
patent: 5229629 (1993-07-01), Koike
patent: 5416347 (1995-05-01), Katto et al.
patent: 5488585 (1996-01-01), Kim
patent: 5512766 (1996-04-01), Kusunoki et al.
patent: 5521541 (1996-05-01), Okamura
patent: 62-180594 (1987-08-01), None
Kiyoo Ito, VSLI Memory, Baifukan Press, pp. 19, 132 and 133. Semiconductor Memories, Betty Prince, Wiley Publishers, pp. 170-171, and 472-473.
Arimoto Kazutami
Sakashita Narumi
McDermott & Will & Emery
Meier Stephen D.
Mitsubishi Denki & Kabushiki Kaisha
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