Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-08-18
2002-04-16
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S614000
Reexamination Certificate
active
06372623
ABSTRACT:
This invention relates to the fabrication and assembly of semiconductor chips, substrates, and modules, and more particularly to methods and apparatus for achieving flexible, low-cost manufacturing. Commercial and military systems today are placing increasing demands on flexible application and reliable operation, as well as on simplified manufacturing.
BACKGROUND OF THE INVENTION
Semiconductor devices have been prepared in the past using various combinations of metallization over the circuit metal contact pads. Such combinations generally have included the use of thin films of refractory metals as well as gold and palladium, which require costly patterning steps involving hazardous material and chemical waste, and also generate stress in the semiconductor chips. They furthermore severely limit the choice of soldering materials for assembly and packaging. Although platinum, with titanium as undermetal, has been proposed in 1996 (“Self-Aligned, Fluxless Flip-Chip Bonding Technology for Photonic Devices”, by J. F. Kuhmann, H.-J. Hensel, D. Pech, P. Harde, and H.-G. Bach, Proc. 1996 Electronic Components and Technology Conference, May 1996), it was restricted to specialty III-V photonic devices and eutectic solder connections. For rerouting processes on semiconductor circuits, past technology offers only methods of questionable effectiveness to position the thin metal films across the sides or edges of the chip. In addition, the patterning processes for these thin metal films are expensive and generate liquid waste byproducts which must be disposed of. For forming cubes from a plurality of stacked chips, the known technology must rely on cumbersome, expensive methods. Known methods for assembling individual chips or finished cubes onto substrates often involve poorly compatible metallization and solders, with difficulty for aligning active parts and substrate.
In summary, the goal of offering for commercial and military systems cost-effective, reliable, rerouted semiconductor products, manufactured in high volume and with flexible, low-cost production methods, has remained elusive, until now.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided first a plurality of silicon semiconductor devices for application in digital signal processing, microprocessor, memory and other commercial and military applications requiring flexibility, high reliability and cost-effectiveness; secondly a process aiming at low-cost manufacturabilty, far reduced number of process steps and easy rework, all of which offer an economic advantage over the prior art and also avoid the generation of chemical waste byproducts which would require costly disposition; and thirdly, apparatus is provided for improving selected steps of the process.
It is an object of the present invention to provide a low-cost method and system for rerouting the circuit metal contact pads.
Another object of the present invention is to provide a method for wide assembly flexibility by using reroute metal and solder material combinations allowing a wide range of assembly temperatures.
Another object of the present invention is to simplify system rework by employing simultaneously various solder/material combinations.
Another object of the present invention is to provide a method for patterning the reroute metal so that it can operate cost-effectively in two as well as in three dimensions.
Another object of the present invention is to provide a technology for covering the small sides or edges of the chips in preparation for reliable extension of the reroute network across said small sides.
Another object of the present invention is to provide a method and apparatus for cost-effectively laminating semiconductor chips in a three-dimensional configuration to allow high density packaging.
Another object of the present invention is to provide a plurality of conductive means on the interconnect substrate compatible with the chip conductors and solder material choices.
Another object of the present invention is to develop a flexible, efficient, economical, mass producible technology for dense packaging of semiconductor chips.
These objects have been achieved by a mass-production process using a combination of thin film platinum metallization, protective dielectric masking, and three-dimensional laser ablation, in conjunction with a variety of solder combinations and melting temperatures. These combinations have been employed for the fabrication of silicon chips as well as connective substrates. Furthermore, spacing films with adhesive properties on both surfaces have been successfully used for assembling multi-chip cubes.
Other objects and features of the invention will become more readily understood from the following detailed description and appended claims when read in conjunction with the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof.
REFERENCES:
patent: 5567981 (1996-10-01), Bhansali et al.
patent: 5648686 (1997-07-01), Hirano et al.
Hoffman Emily Ellen
Terrill Robert E.
Wolverton Wesley Michael
Honeycutt Gary C.
Navarro Arthur I.
Telecky Fred
Texas Instruments Incorporated
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