Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-01-18
2002-03-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S118000
Reexamination Certificate
active
06352935
ABSTRACT:
1. FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to a method of mounting a protective cover on a semiconductor wafer substrate on which one or more devices have been fabricated.
2. BACKGROUND OF THE INVENTION
It is possible to implement many types of devices on a semiconductor wafer using known processes. Typically, multiple devices are implemented on a single semiconductor wafer and then are separated into individual components by sawing the wafer into multiple parts (“dicing”), each part containing one or more devices. To avoid excessive heat build-up on the wafer and to prevent the devices from being damaged by heating which may occur during dicing, it is conventional to spray the wafer with water or another type of liquid to cool the wafer during the dicing process.
For many types of devices, using liquid to cool the wafer during the dicing process does not affect the function of the device after dicing has been completed. However, other semiconductor devices are extremely fragile and/or sensitive to, and may be negatively affected by, environmental hazards, such as dust or other particulates, moisture, and inadvertent scratching, collectively “contaminants.”
One example of a device that may be adversely affected by being exposed to contaminants during the dicing process is a micro-mechanical structure, useful, e.g., as an acceleration or pressure sensor. A typical micro-mechanical structure has a cantilevered beam or other structure that resides above the surface of the substrate. Movement of the beam of the micro-mechanical structure relative to the base may be used to determine a physical variable, such as acceleration or pressure. Particulate matter or moisture may impede movement of the micro-mechanical structure or may otherwise adversely affect generation of a signal from movement of the micro-mechanical structure.
As a result, it has become common in the industry to protect micro-mechanical structures and other devices resident on a semiconductor substrate after fabrication to prevent active areas of the semiconductor substrate from becoming contaminated during subsequent processing. As used herein, the term “active area” will be used to refer to that portion of a semiconductor substrate that should be or is desired to be protected from contamination. An “active area” as that term is used herein may, but need not, include a micro-mechanical structure. Multiple active areas may be formed on a single wafer.
There are several known techniques that may be used to protect the active area of a semiconductor substrate during processing. One method involves placing several layers of protective tape over the active areas to prevent the active areas from being contaminated. In this method, a first layer of tape having holes corresponding to the locations of the active areas is initially applied to the wafer and then a second layer of tape is applied over an exposed surface of the first layer of tape. This method requires the wafer to be diced from the back side of the wafer instead of the front side of the wafer, which makes it more difficult to align the dicing saw so that the dicing saw does not cut through the active areas on the wafer. An exemplary saw usable in this context is disclosed in U.S. Pat. No. 5,356,681, the content of which is hereby incorporated by reference. Moreover, the tape requires substantial surface area to be effective, thus reducing the density of active areas on the semiconductor. As used herein, the term density will be used to refer to the number of active areas per unit area that may be formed on any one wafer.
A second known technique of protecting active areas of the silicon wafer is to apply a protective cap wafer to an exposed surface of the semiconductor substrate containing the active areas prior to dicing. Typically, the protective cap wafer is sealed to the semiconductor substrate with a lead oxide glass frit or another sealant. This sealant is screen printed on the cap and then bonded to the semiconductor substrate under heat and pressure to form individual hermetic seals around an active area on the semiconductor substrate. The micro-mechanical structures or other devices in the active areas are sealed below the cap wafer and are free to move, yet are protected from the external environmental hazards. This technique is advantageous in that it allows standard front side dicing to be used to separate the semiconductor wafer into individual elements. Screen printing lead oxide glass frit also uses less surface area than the tape method, thus increasing density.
Unfortunately, constraints associated with screen printing limit the accuracy with which the sealant may be deposited on the cap and the minimum width of the lines that may be formed. Thus, although screen printing sealant is better than using the tape method, limitations attendant to screen printing require the sealant to occupy an overly large area on the semiconductor wafer, thus limiting the overall yield achievable with this method.
For example, as shown in
FIG. 1
, screen printing sealant results in a relatively thick line
100
of sealant. Specifically, using current technology, the minimum line width achievable using screen printing is about 150 &mgr;m. Moreover, screen printing does not permit interior comers
105
to be accurately defined, thus necessitating an offset between an interior edge of the line of sealant and the outer edge of the active area, shown in dashed lines in FIG.
10
. Finally the width of the sealant is limited by inherent inaccuracies in the screen printing process. For example, if a line of sealant with a width of 150 &mgr;m is printed, the variation in line width may be up to approximately 25 &mgr;m.
Photolithography has been attempted, unsuccessfully, as a method to reduce the width of lines of sealant. For example, one attempt at using photolithography is set forth in
FIGS. 2
a
-
2
e
. In this method, a sealant
30
is first screen printed on the silicon cap wafer
28
incurred. Subsequently, as shown in
FIG. 2
b
, a photoresist
32
is then applied over the sealant
30
and patterned, as shown in
FIG. 2
c
, to define regions where it would be desirable to have sealant
30
remain on the silicon cap wafer
28
after subsequent processing. The sealant
30
then is etched, as shown in
FIG. 2
d
, to remove excess sealant
30
from the areas other than where desired for sealing the silicon cap wafer
28
to a semiconductor wafer including active devices. After the excess sealant
30
has been removed, the remaining photoresist
32
is removed to produce a silicon cap wafer
28
carrying areas of sealant
30
defined by photolithography, as shown in
FIG. 2
e.
This method has proven satisfactory for depositing lines of solder sealant and other sealants for which acceptable etchants have been developed. Unfortunately, however, solder is unsuitable for many applications because of a mismatch between the coefficient of thermal expansion between typical solders and semiconductor substrates, which can cause the wafer to warp or crack. It is thus necessary to use a material, such as lead oxide glass, with a coefficient of thermal expansion that more closely matches the coefficient of thermal expansion of the substrates. Since lead oxide glass is a two-phase mixture, however, applicants have found that known etchants will attack preferentially only one phase of the two-phase mixture forming the lead-oxide glass resulting in a rather jagged line of sealant. Accordingly, it is not generally possible to etch two phase sealants such as lead-oxide glass.
Another attempt to optically define lines of sealant is illustrated in
FIGS. 3
a
-
3
b
. According to this embodiment, a photoresist and sealant mixture
38
is first coated on the silicon cap wafer
28
(
FIG. 3
a
) and then patterned (
FIG. 3
b
) to define regions where the sealant will remain after firing. The sealant and photoresist mixture
38
is hardened by firing or baking to remove excess solvent. One potential sealant/photoresist mixture
3
Collins David J.
Core Craig E.
Felton Lawrence E.
Luo Jing
Analog Devices Inc.
Lee Calvin
Wolf Greenfield & Sacks P.C.
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