Semiconductor memory device with internal power supply...

Details Semiconductor memory device with internal power supply... Semiconductor memory device with internal power supply...

2001-04-09

2002-07-23

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S226000

Reexamination Certificate

active

06424579

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a semiconductor memory device including a potential generation circuit generating an internal power supply potential based on an external power supply potential.
2. Description of the Background Art
In dynamic random access memories (referred to as “DRAM” hereinafter), reduction in the internal power supply voltage is conventionally aimed as well as realizing microminiaturization and high integration of the structural elements.
FIG. 19
is a circuit block diagram showing the main part of such a DRAM. In the DRAM of
FIG. 19
, a voltage-down converter (referred to as VDC hereinafter)
70
down-converts an external power supply potential EXVCC to generate and provide to a sense amplifier
73
an internal power supply potential VCCS. VDC
71
down-converts external power supply potential EXVCC to generate and provide to a row decoder
72
, a column decoder
75
and a data input/output buffer
76
an internal power supply potential VCCP. Each memory cell MC includes an N channel MOS transistor Q for access and a capacitor C for information recording. Row decoder
72
selects a word line WL out of a plurality of word lines WL. That word line WL is set to an H level (logical high) of the selected level. Accordingly, N channel MOS transistor Q of memory cell MC connected to that word line WL conducts, whereby a small potential difference is generated between a pair of bit lines BL and /BL that is already equalized to a bit line potential VBL.
The small potential difference generated between the pair of bit lines BL and /BL is amplified by sense amplifier
73
to internal power supply voltage VCCS. When a column select line CSL is driven to an H level (internal power supply potential VCCP) of the selected level by column decoder
75
, a pair of N channel MOS transistors in column select gate
74
conducts, whereby the voltage between bit lines BL and /BL is transmitted to a pair of data input/output lines IO and /IO. Data input/output buffer
76
outputs externally a signal of a logic level corresponding to the voltage between the pair of data input/output lines IO and /IO (+VCCS or −VCCS) as readout data.
FIG. 20
is a block diagram showing a structure of a DRAM mounted on one chip together with an ASIC circuit (referred to as eDRAM hereinafter). Referring to
FIG. 20
, VDC
81
a-
81
d
are under control of a VDC activation signal VDCON to down-convert external power supply potential EXVCC to generate an internal power supply potential VCCS. Internal power supply potential VCCS is applied to each sense amplifier band SA and column decoder
84
in a memory mat
82
. The peripheral circuits such as row decoder
83
, data input/output buffer
85
and control circuit
86
are driven by internal power supply potential VCC for the ASIC circuit. The reason why column decoder
84
is driven by internal power supply potential VCCS for sense amplifier band SA is that, if column decoder
84
is driven by internal power supply potential VCC, data cannot be transferred between bit line pair BL and /BL and data input/output line pair IO and /IO shown in
FIG. 19
since internal power supply potential VCC of the ASIC circuit is reduced to 1.2 V whereas internal power supply potential VCCS of sense amplifier band SA is approximately 2 V.
FIG. 21
is a circuit diagram showing a structure of VDC
81
a.
Referring to
FIG. 21
, VDC
81
a
includes P channel MOS transistors
90
-
93
and N channel MOS transistors
94
-
96
. MOS transistors
90
,
91
and
94
-
96
form a differential amplifier
97
that compares a reference potential VREF with an internal power supply potential VCCS.
Signal VDCON attains an H level of an activation level and an L level of an inactivation level in response to the input of an active command ACT and a precharge command PRE, respectively. When signal VDCON is at an L level of an inactivation level, P channel MOS transistor
92
is rendered conductive whereas N channel MOS transistor
96
is rendered nonconductive. Driver transistor
93
is fixed at the nonconductive state, and differential amplifier
97
is rendered inactive.
When signal VDCON attains an H level of an activation level, P channel MOS transistor
92
is rendered nonconductive whereas N channel MOS transistor
96
is rendered conductive, whereby differential amplifier
97
is activated. When internal power supply potential VCCS is lower than reference potential VREF, P channel MOS transistor
93
conducts to supply current to an output node N
93
. When internal power supply potential VCCS is higher than reference potential VREF, P channel MOS transistor
93
is rendered nonconductive, whereby the supply of current to output node N
93
is ceased. Therefore, internal power supply potential VCCS is maintained at the level of reference potential VREF. Other VDC
81
b-
81
d
have a structure identical to that of VDC
81
a.
In the above-described eDRAM, column select line CSL is selected immediately after activation of the sense amplifier in the read and write operations. Furthermore, current consumption of column decoder
84
is great since the number of IOs is greater than that of a general purpose DRAM. Therefore, internal power supply potential VCCS will become lower than reference potential VREF unless the current supply capability of VDC
81
a-
81
d
is set large enough.
In order to increase the current supply capability of VDC
81
a-
81
d,
the size of driver transistor
93
is to be increased. However, simply increasing the size will degrade the response since the gate capacitance of transistor
93
becomes larger. In order to improve the response, the through current I flowing to N channel MOS transistor
96
must be increased.
FIG. 22
is a timing chart of through current I in VDC
81
a-
81
d.
There is the possibility of a read command READ or a write command WRT input to effect a column select operation during the amplify operation of sense amplifier
73
in response to the input of an active command ACT. Therefore, through current I is set to a constant I=Is+Id during the period of input of active command ACT up to input of precharge command PRE, where Is is the through current required during the amplify operation of sense amplifier
73
and Id is the through current required during a column select operation.
However, through current I is set to I=Is+Id even in an active standby state where neither an amplify operation of sense amplifier
73
nor a column select operation is carried out. Current consumption was wasted greatly in conventional cases.
SUMMARY OF THE INVENTION
In view of the foregoing, a main object of the present invention is to provide a semiconductor memory device of small current consumption.
According to an aspect of the present invention, a semiconductor memory device includes a first potential generation circuit generating a first internal power supply potential for a sense amplifier according to an external power supply potential, and a second potential generation circuit generating a second internal power supply potential for a column select circuit according to the external power supply potential. At least one of the first and second potential generation circuits has a controllable response with respect to change in the output potential during the activation period. By increasing the response of the first and/or second potential generation circuit during the period where current consumption of the first and/or second internal power supply potential is great, and lowering the response of the first and/or second potential generation circuit during other periods, the current consumption of the first and/or second potential generation circuit can be reduced. Thus, the current consumption of the semiconductor memory device can be reduced.
Preferably, the first potential generation circuit includes a first transistor connected between a line of the external power supply potential and a line of a first internal power su

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