Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-12
2002-01-08
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S332000, C257S334000
Reexamination Certificate
active
06337498
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device and a semiconductor device manufacturing method, and in particular to an insulated gate type semiconductor device which has plural gate electrodes, and a method of manufacturing this device.
Hitherto, an IGBT (Insulated Gate Bipolar Transistor) has been well known as an insulated gate type semiconductor device which has plural gate electrodes. In the IGBT, from the standpoint of its ON-state resistance, turn-off loss, limit breaking current and the like, a trench gate structure in a stripe form has been frequently adopted as a gate electrode.
FIG. 6
schematically illustrates a conventional IGBT in which a trench gate structure in a stripe form is adopted.
In this IGBT
100
, for example, a P-type base layer
103
is deposited on an N-type base layer
101
of a silicon substrate wherein a P-type emitter layer is disposed beneath the N-type base layer
101
. Plural N-type source areas
104
are selectively positioned in the surface portion of this P-type base layer
103
.
Moreover, In the surface portion of the P-type base layer
103
, trenches
105
are selectively formed, each of which penetrates into the N-type source areas
104
and the P-type base layer
103
and has such a depth that the trenches reach the N-type base layer
101
. The respective trenches
105
are in a form of stripes extending in a direction perpendicular to the illustrated sectional direction and have substantially the same length.
Resistance-reduced polysilicon is embedded through insulated gate films
106
in the respective trenches
105
, so that respective trench type gate electrodes (trench gates)
107
are formed. An insulated oxide film
108
is deposited on each of upper portions of the trench gates
107
, including a portion of the upper surface of the N-type source area.
Furthermore, an emitter electrode
109
is disposed on the upper portion or the P-type base area
103
, including the upper portion of the insulated oxide film
108
, so as to cover the whole of their upper surfaces. Additionally, a collector electrode
110
is disposed beneath the P-type emitter layer
102
of the silicon substrate.
Incidentally, as shown in, for example,
FIG. 7
, in the IGBT
100
having such a structure, the respective trench gates
107
are formed on the silicon substrate extending parallel to each other in the same direction.
Specifically, the inside of a terminal area
201
of the IGBT
100
is divided into, for example, a single gate pad area
201
a
and a plurality (three in this case) of element areas
201
b
. A wiring area
201
c
for leading polysilicon wirings from the gate pad area
201
a
is composed between the manual element areas
201
b.
In the respective element areas
201
b
, usually, the respective trenches
105
are formed so that the directions of the trench gates
107
are along the same direction (in this case, the horizontal direction in FIG.
7
), from the standpoint of capability of bonding to the polysilicon wirings. (For example, a section along the line a in
FIG. 7
corresponds to
FIG. 6.
)
However, the IGBT
100
having the aforementioned structure is, in the process for manufacturing the IGBT, subjected to heat treatment, e.g., in the process of forming insulated oxide film
108
wherein phosphorus gathering after CVD deposition is performed, at high temperatures up to 900°-950° C. after polysilicon is embedded in the trenches
105
. At this time, a stress is generated between the polysilicon and the silicon substrate because polysilicon is embedded in the trenches
105
. A residual stress remains even after the temperature of the IGBT
100
is returned to ordinary temperature.
The arrangement pitch L
1
(see
FIG. 6
) of the trench gates
107
in the sectional direction is about 5 &mgr;m and crosses the sectional direction at right angles. The length of the trench gates
107
in their stripe direction is about several millimeters. In this case, the stress in the sectional direction (the illustrated arrow A direction) perpendicular to the trench gates
107
in equal to the total of the stresses at the respective trench gates
107
, and is stronger than the stress in the stripe direction parallel to the trench gates
107
(the illustrate arrow B direction). This occurs because the area of junction between silicon and polysilicon is greater in the A direction than in the B direction and more trench gates are formed in the A direction than in the B direction.
Therefore, in particular, in the case of the IGBT
100
having a large area and a large number of the trench gates
107
, there remains a problem that a leakage current and crystal defects are liable to arise because of the stress concentrating in the sectional direction (the illustrated arrow A direction) perpendicular to the trench gates
107
.
In manufacturing such a type IGBT
100
, as shown in
FIG. 8
, for example, generally plural IGBT pellets (P)
301
are formed on a single wafer
300
which is then divided for each of the IGBT pellets
301
, resulting in obtaining the plurality of IGBTs
100
at the same time.
Conventionally, however, the respective IGBT pellets
301
have been formed on the wafer
300
, so as to be wholly along the same direction (shown schematically in
FIG. 8
by the orientation of “P”). In other words, the plural IGBTs
100
having trench gates
107
along the same direction have been formed in the same direction (in this case, the direction of the trench gates
107
coincides with the illustrated arrow B direction) on the wafer
300
. The internal stress in the A direction illustrated in
FIG. 7
is greater than that in the B direction in relation to the difference in sectional area of junction lines between silicon and polysilicon in the A and B directions, and in relation to the greater number of trench gates in the A direction than in the B direction.
For this reason, in particular where the diameter of the wafer
300
is large, the wafer
300
bends very much due to the stress concentrating in the sectional direction (the illustrated arrow A direction) perpendicular to the trench gates
107
, as described above. This bend in the wafer disturbs subsequent treatments in the manufacturing process.
As described above, In the conventional IGBT, all of the trench gates are formed so that their directions are along the same direction, and consequently the stress in the direction perpendicular to the trench gates is stronger than the stress in the stripe direction. Thus, problematic leakage current and crystal defects arise by the strong stress in the direction perpendicular to the trench gates.
Moreover, in conventional IGBT manufacturing methods, there arises a problem that a wafer bends very much by the strong stress in the direction perpendicular to trench gates.
BRIEF SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor device in which concentration of stress in only a single direction is relieved and generation of a leakage current and crystal defects is prevented.
Furthermore, another object of the present invention is to provide a semiconductor device manufacturing method making it possible to relieve concentration of stress only in a single direction and prevent a wafer from bending very much.
To attain the aforementioned object, a semiconductor device of this invention includes plural gate electrodes formed in parallel to each other in element areas in a single substrate, with the gate electrodes formed in such a manner that stresses generated between the substrate and the gate electrodes are substantially directionally balanced inside the substrate. To that end, the gate electrodes disposed in parallel to each other are arranged on a single substrate in such a manner that directions of the gate electrodes in adjacent element areas cross each other at angles, such as right angles, so as to balance stresses directionally within the wafer. Of importance is that stresses are not concentrated in a single direction but are balanced. This can be achieved by having dir
Baba Yoshiro
Hasegawa Shigeru
Matsuda Hideo
Tsuchitani Masanobu
Loke Steven
Owens Douglas W.
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