Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1999-09-14
2002-07-16
Flynn, Nathan (Department: 2816)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S667000, C257S669000, C257S670000, C257S676000
Reexamination Certificate
active
06420779
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit packaging, and more particularly to leadframe based chip scale packaging of integrated circuits.
2. Related Art
A desire to reduce the size of electronic devices has resulted in the a demand to increase the mounting density of integrated circuits (ICs) on printed circuit boards (PCBs). This demand has spurred the development of new technologies designed to reduce the difference between the PCB area required to mount an IC and the area of the IC chip itself. One such technology involves using a molded package where the leads do not extend, or extend only slightly beyond the area of the package.
A first approach to this technology is illustrated in
FIG. 2
of U.S. Pat. No. 5,519,251 (hereafter '251), entitled “Semiconductor Device And Method Of Producing The Same” According to this approach, the length of the leads projecting outside the edges of the package is reduced by exposing a bottom surface of a portion of each lead at the bottom of the package. Another approach, offering a reduced package area, is described in the above mentioned U.S. Patent, as well as in U.S. Pat. No. 5,363,279 (hereafter '279) and 5,428,248 (hereafter '248), entitled “Semiconductor Package For A Semiconductor Chip Having Centrally Located Bottom Bond Pads” and “Resin Molded Semiconductor Package”, respectively. This approach is known as “chip on lead” (COL), because the chip is positioned on top of an inner portion of the leads, so that the outer ends of the leads, and therefore the edges of the package, can be moved closer to the center of the die. One goal of this type of approach is the design of a “chip scale package” (CSP), so called because the area of the package is approximately the same as, or slightly larger than, the area of the chip.
There are a number of disadvantages to each of these prior approaches. In addition to having the disadvantage of a greater package area than the latter mentioned approaches, the first approach (
FIG. 2
of '251) has the disadvantage that an efficient means for dissipating heat generated from the IC chip is lacking. This heat dissipation disadvantage is also shared by the approaches of '279 and '248. While the approach of '251 adds a stage or die pad to improve the heat dissipation efficiency, this approach requires the use of two lead frames, necessitating a more complex and expensive assembly process. Also, the approaches of '279 and '259 require that the bond pads to which the leads are electrically connected be positioned in the center of the die, rather than around the outside edge of the die. This requirement generally adds complexity and area to the layout of the die. Finally, all four of these approaches suffer from the disadvantage that the exposed portions of the leads are exposed by virtue of being coplanar with the bottom surface of the molding compound. Therefore, these approaches are susceptible to a manufacturing problem known as “mold flash”, where during the molding process, some of the molding compound bleeds out over the portions of the leads intended to be completely exposed.
The mold flash problem can addressed by adding a process step to remove the mold flash. However, the addition of this step adds process complexity and does not always completely clear off the exposed portions of the leads, resulting in the potential for unreliable mechanical, electrical, and thermal connections between the leads and the PCB. Therefore, two other approaches have been developed. One of these is described in U.S. Pat. No. 5,656,550 (hereafter '550), entitled “Method Of Producing A Semiconductor Device Having A Lead Portion With Outer Connecting Terminal”, and U.S. Pat. No. 5,900,676 (hereafter '676), entitled “Semiconductor Device Package Structure Having Column Leads And A Method For Production Thereof”. According to each of these approaches, the leads are exposed through the bottom of the package, but the are not coplanar with the bottom of the package. Therefore, the mold flash problem can be reduced. However, both of these approaches require additional process steps to achieve this result.
In response to the aforementioned disadvantages of these prior approaches, a novel leadframe based CSP and its method of production have been developed.
SUMMARY OF THE INVENTION
A novel electronic device and its method of production are disclosed. The device includes an integrated circuit chip, a die pad, leads, and a molding compound. The chip is affixed to the top surface of the die pad. The leads are connected to the chip, and the top surface of each lead is flat. The molding compound encapsulates the chip, die pad, and leads such that the bottom surface of the die pad and the bottom surface of each lead is exposed and coplanar with the bottom surface of the molding compound.
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Konishi, S., et al., “OFN (Quad Flat Non-Leaded Package),” 4th Symposium on “Microjoining and Assembly Technology in Electronics,” Japan Welding Society (Committee of Microjoining), Yokohama, Jan. 29-30, 1998, pp. 149-152 (in Japanese, with English translation).
Bidin Rahamat
Sharma Nirmal K.
Tan Hien Boon
Laurie Ronald S.
Ramos Constance F.
Skadden, Arps
ST Assembly Test Services Ltd.
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