Memory control device with split read for ROM access

Details Memory control device with split read for ROM access Memory control device with split read for ROM access

1997-04-07

2002-01-01

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S102000, C711S005000

Reexamination Certificate

active

06336166

ABSTRACT:

BACKGROUND
The present invention relates to an apparatus for accessing data from a computer memory device. More particularly, the present invention relates to an apparatus that employs a dual cache line buffer for accessing read only memory (ROM) data, wherein the dual cache line buffer is a separate and independent data path from the data path that is used to transport data to and from the random access memory (i.e., the RAM or DRAM).
FIG. 1
illustrates a conventional computer memory system
100
. In
FIG. 1
, the microprocessor
103
sends and receives data and/or instructions to and from memory via system bus
105
, a memory interface device
110
, and one or more memory buses
115
a
and
115
b
.
FIG. 1
also shows that the memory bus utilized for carrying ROM data is a common bus, such that it is shared, at least in part, with the memory bus (e.g., memory bus
115
b
) which carries data to and from DRAM.
For some conventional computer systems, a common memory bus that is shared by the RAM and the ROM is not a significant hindrance. That is because these computer systems do not store a large portion of their operating systems in ROM. Consequently, these systems do not access the ROM as often as other systems. In contrast, there are other computer systems that do store a large portion of their operating systems in ROM. Hence, these other systems access ROM more frequently, and the common memory bus architecture is problematic for these other systems.
The primary reason the common memory bus architecture is problematic for systems that frequently access ROM is that ROM devices are inherently slow. For example, a typical ROM burst access requires approximately 20 to 30 clock cycles. If the system clock is operating at 50 MHz (i.e., with a 20 nanosecond clock cycle), a complete ROM access period requires approximately 400 to 600 nanoseconds to complete. This means that the memory bus, e.g., memory bus
115
b
, is occupied with the task of accessing the ROM for at least 400 nanoseconds. Moreover, the system bus
105
will also sit idle for a substantial portion of the at least 400 nanosecond period, waiting to receive the ROM data from the memory bus
115
b
. Accordingly, both the system bus
105
and the memory buses
115
a
and
115
b
are precluded from conducting any other operations during the 400 nanosecond ROM access period. Such systems must, therefore, serialize all memory operations with ROM operations. Of course, this is inefficient since it slows down system operations and hinders system performance. Consequently, there is a need to provide a memory architecture design that minimizes the detrimental impact on system performance caused by frequent ROM access operations using a common memory bus architecture.
SUMMARY
The present invention is a computer memory access and control system which includes a cache line buffer for ROM and an independent ROM bus. More specifically, the present invention, in accordance with a preferred embodiment, actually employs two dual cache line buffers for ROM. In addition, the independent ROM memory bus is separate from and distinctly different than the RAM buses (or DRAM buses).
One advantage provided by the present invention is that the system bus and the RAM buses are now free to perform other tasks, e.g., data write and data read operations to and from DRAM, during a significant portion of the ROM access period. Another advantage is that the present invention is capable of pre-fetching ROM data from a next ROM address and storing that data in a second cache line buffer, thus further accelerating ROM operations and enhancing system performance.
In general, the dual cache line buffer for ROM provides a timing windfall equal to approximately 20 clock cycles (i.e., 400 nanoseconds) for each ROM access operation. For computer systems that frequently access ROM, the timing windfall realized, when accumulated over a large number of ROM access operations, is significant.
In view of the above, it is an object of the present invention to enhance system performance by employing an independent ROM data path.
It is yet another object of the present invention to enhance system performance by storing the ROM data in one of two cache line buffers until the system bus is available to receive the data, thus freeing the system bus and the memory bus to engage in other operations during a significant portion of each ROM access period.
In accordance with one aspect of the present invention, the foregoing and other objects are achieved by a computer system comprising a processing unit; a random access memory (RAM) connected to the processing unit by a RAM data path; and a read only memory (ROM) connected to the processing unit by a ROM data path. In this system, the ROM data path is separate and independent of the RAM data path.
In accordance with another aspect of the present invention, the foregoing and other objects are achieved by a computer memory access and control system comprising a processing unit; memory access control means connected to the processing unit by a first data bus; a random access memory connected to the memory access control means by a second data bus; and a read only memory (ROM) connected to the memory access control means by a third data bus. Here, the third data bus is separate and independent of the second data bus.
In accordance with yet another aspect of the present invention, the foregoing and other objects are achieved by a computer memory access and control system comprising a microprocessor; a first memory access control integrated circuit (IC) connected to the microprocessor by a system data bus; a random access memory (RAM) connected to the first memory access control IC by a RAM bus; and a read only memory (ROM) connected to the first memory access control IC by a ROM bus. Again, the ROM bus is separate and independent of the RAM bus.
In accordance with still another aspect of the present invention, the foregoing and other objects are achieved by a method of transferring data from a ROM to a system processor comprising the steps of transferring ROM data from a memory address in the ROM to a cache line buffer for ROM; accessing the system bus after the data has been transferred to the cache line buffer for ROM; transferring the data from the cache line buffer for ROM onto a system data bus that is connected to the system processor. In this method, the step of transferring data from a memory address in ROM to a cache line buffer for ROM can occur simultaneous to data transfers between the system processor and the RAM.


REFERENCES:
patent: 5317720 (1994-05-01), Stamm et al.
patent: 5388841 (1995-02-01), San et al.
patent: 5579277 (1996-11-01), Kelly
patent: 5719808 (1998-02-01), Harari et al.
patent: 5784291 (1998-07-01), Chen et al.
patent: 5936971 (1999-08-01), Harari et al.

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